Principal ASIC Design Engineer

This role is for a ASIC design Lead for deep submicron technology with strong experience in end-to-end ASIC development, microarchitecture definition, RTL design, and technical leadership. The role requires ownership of a major ASIC/function from requirements analysis through implementation, verification, and silicon qualification.Experience with low-power ASIC design techniques and clock domain crossing
Knowledge of AMS verification methodologies
Exposure to silicon bring-up and lab validation
Familiarity with EDA tools from Synopsys, Cadence, or Mentor
Candidate must have a bachelor's degree or higher in CS or EE with very good academics. Master's degree preferred
10+ years of experience and hands-on experience in delivery of a major function/ASIC
Preferred: Prior experience in Ethernet/Networking domain
Ability to mentor and bring together engineers with differing but valid technical viewpoints
Ability to interpret and map documents from standard bodies to requirements/functions
Work with the architecture and other cross functional teams like SDK, verification, emulation teams.
Ability to comprehend high level requirements and create a microarchitecture document
Provide technical leadership to a team of designers and be responsible for delivery by taking it through planning, definition and implementation phase.
Handson experience with various aspects of ASIC design including RTL coding and design checks including lint, CDC, RDC, synthesis
Strong design skills - should be able to review the arch, requirements and micro-arch, synthesis and timing reports.
Work with verification and lab validation teams to debug and qualify the implementation.

Work arrangement
Hybrid