Live opening · Posted 9 hours ago
Senior Principal Engineer
NXP Semiconductors · Noida
JobBeeper subscribers received an alert for this role.
At a glance
The key details from the original listing.
CompanyNXP Semiconductors
LocationNoida
Source
Workday
ListedPosted 9 hours ago
Your early-applicant advantage
Live timing from JobBeeper.
1 min
from Workday publishing this role to us finding it
26 min
median time from a role going live to a subscriber being told
6 hours
subscribers had this role before this page existed
43,052
roles found in the last 24 hours — the newest are not on this site yet
About the role
Description supplied by the original job listing.
Job Description
Digital Design Engineer with hand on experience in Scan insertion, ATPG, GLS. And will be responsible for understanding the DFT architecture of the design and providing the scan insertion collaterals to the implementation team, to enable scan insertion flows during synthesis.
Should have proficiency in industry-standard DFT tools such as Mentor Tessent, Synopsys DFT Compiler, Cadence Encounter Test. Should be able to contribute to ATPG at partition and SoC level. .
Should have experience with DFT GLS simulation tools and methodologies, including fault modeling and coverage analysis. Should be familiar with industry standards such as IEEE 1149.1 (JTAG) and IEEE 1687 (IJTAG).
Effective communication and teamwork skills, with the ability to collaborate across functions.
#LI-DNI
More openings worth a look
Recently tracked roles with full details and direct application links.
Good roles move before most people even see them.
Tell JobBeeper what you want and get fresh matches delivered in minutes.
Start your free trial →