Sr. Staff Engineer, ASIC Physical Design

Location: Bangalore (on-site, flexible hours)
Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we are using light instead of electricity to move data faster, further, and with a fraction of the energy needed to fuel the explosive growth of AI models.
Backed by industry giants like NVIDIA, AMD and Intel and manufactured in partnership with the world’s leading semiconductor ecosystem, Ayar Labs’ co-packaged optics solution is key to unleashing next-generation AI scale-up architectures.
The ASIC Physical Design Engineer is responsible for the physical design and integration of complex SoCs with custom circuits, digital circuits, and photonics components as part of a high-speed electro-optical engine. The position focuses on the synthesis, place and route, timing closure, and physical verification steps of the design implementation process.
This PD Engineer is expected to take on full end-to-end responsibility for the implementation of complex blocks integrating both high-speed digital and custom blocks in leading edge process nodes.
Key Responsibilities
Physical design of blocks containing digital and custom analog / mixed-signal blocks
Contribute to design for test (DFT) methodologies
Contribute to automated design methodologies for ASIC physical design
Perform ASIC physical design (synthesis, place-and-route), static timing analysis (STA), and physical verification (DRC/LVS) of mixed-signal SoCs
Coordinate and drive activities across multiple designers
Contribute across a broad range of CAD methodologies to improve design implementation flows
Basic Qualifications
BS or MS in Electrical Engineering, Computer Engineering, or related fields
5+ years of work experience in ASIC physical design
History of leading successful block implementations integrating custom IP in leading edge process nodes
Proficient in Verilog RTL
Mastery of ASIC synthesis (RTL Compiler, Genus, Design Compiler), place-and-route (Encounter, Innovus, ICC), and physical verification (DRC, LVS) tools and flows
Mastery of timing constraints and deep understanding of static timing analysis
Proficient in clock tree synthesis methodologies and customization
Proficient in designing DFT methodologies and flows such as scan insertion, BIST, ATPG, etc.
Proficient in ASIC signoff methodologies, checklists, and requirements
Proficient in scripting or programming languages
Preferred Qualifications
Working knowledge of the Cadence Virtuoso design environment for manual schematic entry and layout
Programming experience in Python
Experience with 3DIC implementation methodologies and custom tool flows
Knowledge of high-speed SerDes or SerDes components
Experience working in conjunction with external ASIC services providers
Performed silicon debug and triage of physical design-related issues
Note To Recruiters
Principals only. We are not accepting resumes from recruiters for this position. Remuneration for recruiting activities is only applicable subject to a signed and executed agreement between the parties. Please don’t send candidates to Ayar Labs, and do not contact our managers.

Work arrangement
No