Analog Layout Engineer | 4+ Years

Analog Layout Engineer | 4–10 Years
Company: LeadIC Design Pvt Ltd
Employment Type: Full-time
Workplace Type: Hybrid
Location: Bengaluru,Pune, Hyderabad
Experience: 4–8 years
Notice Period: Immediate to 30 days only
About the Role
LeadIC Design is looking for experienced Analog Layout Engineers with strong expertise in full-custom analog and mixed-signal IC layout, particularly at advanced technology nodes.
The ideal candidate will have hands-on experience with TSMC 2nm, 3nm, 5nm, or 7nm technologies and a solid understanding of device matching, parasitic optimization, physical verification, and tape-out requirements.
Key Responsibilities
Design and implement full-custom analog and mixed-signal IC layouts using Cadence Virtuoso.
Develop precision layouts for analog circuits, ensuring device matching, symmetry, and optimal floorplanning.
Apply common-centroid, interdigitation, shielding, and other layout techniques to minimize mismatch and parasitic effects.
Perform and debug DRC, LVS, ERC, and PEX checks to achieve layout sign-off readiness.
Optimize parasitic resistance and capacitance while meeting performance, area, and reliability requirements.
Collaborate with circuit designers and verification teams to resolve layout-related issues.
Support physical verification, design iterations, and tape-out activities.
Follow process design rules and technology-specific layout guidelines for advanced semiconductor nodes.
Required Qualifications
Experience: 4–10 years of relevant Analog Layout Engineering experience.
Technology: Hands-on experience with TSMC 2nm / 3nm / 5nm / 7nm process nodes.
EDA Tool: Strong proficiency in Cadence Virtuoso.
Layout Expertise: Full-custom analog and mixed-signal IC layout.
Physical Verification: Practical experience with DRC, LVS, ERC, and PEX.
Core Skills: Device matching, common-centroid layout, shielding, parasitic optimization, and layout debugging.
Tape-out: Experience supporting layout sign-off and tape-out activities.
Availability: Must be available to join immediately or within 30 days.
Preferred Skills
Experience working with advanced-node analog or mixed-signal designs.
Understanding of layout-dependent effects, parasitic extraction, and matching-sensitive circuits.
Experience collaborating with analog design and physical verification teams.
How to Apply
Interested candidates who meet the above requirements can send their updated resume to:
Email: nagu.ms@leadicdesign.com
Email Subject: Analog Layout Engineer | Pune/Bengaluru
Please mention your total experience, relevant TSMC technology nodes, current location, and notice period in your application.
Only candidates with relevant advanced-node layout experience and a notice period of 0–30 days will be considered.

Work arrangement
Hybrid