AI Compiler Engineer

Job Requirements
At Quest Global, it’s not just what we do but how and why we do it that makes us different. With over 25 years as an engineering services provider, we believe in the power of doing things differently to make the impossible possible. Our people are driven by the desire to make the world a better place—to make a positive difference that contributes to a brighter future. We bring together technologies and industries, alongside the contributions of diverse individuals who are empowered by an intentional workplace culture, to solve problems better and faster.
Key Responsibilities
As an AI Compiler Engineer on the Renesas HPC team, you will be responsible for driving compiler and code generation technologies that unlock the full compute potential of Renesas next-generation automotive System-on-Chip platforms, including advanced 3 nm silicon for software-defined vehicles (SDVs). Your work will directly impact how AI workloads — from perception and sensor fusion to in-vehicle assistants and advanced driver assistance — are translated into highly optimized, safe, and power-efficient execution on Renesas hardware.
This role bridges software compiler development, AI model lowering/optimization, and hardware-software co-design, enabling Renesas SoCs to deliver industry-competitive performance, efficiency, and functional safety required by multi-domain automotive applications..
Lead AI compiler architecture across model ingestion, graph optimization, lowering, code generation, and runtime integration
・Design and implement graph‑level optimizations (operator fusion, quantization‑aware rewrites, memory‑aware scheduling, partitioning)
・Drive performance optimization for target NPUs, including tiling, tensor layout, and multi‑core execution strategies
・Partner with SoC and AI accelerator architects to influence hardware features through compiler insights
・Own performance KPIs for real automotive AI workloads using simulators, profilers, and silicon‑correlated models
・Ensure compiler outputs meet automotive requirements (real‑time behavior, determinism, quality expectations)
・Mentor senior engineers and set technical direction without people‑management responsibilities
We are known for our extraordinary people who make the impossible possible every day. Questians are driven by hunger, humility, and aspiration. We believe that our company culture is the key to our ability to make a true difference in every industry we reach. Our teams regularly invest time and dedicated effort into internal culture work, ensuring that all voices are heard.
We wholeheartedly believe in the diversity of thought that comes with fostering a culture rooted in respect, where everyone belongs, is valued, and feels inspired to share their ideas. We know embracing our unique differences makes us better, and that solving the worlds hardest engineering problems requires diverse ideas, perspectives, and backgrounds. We shine the brightest when we tap into the many dimensions that thrive across over 21,000 difference-makers in our workplace.
Work Experience
Renesas’ Gen5 R-Car automotive SoC lineup, including flagship 3 nm devices like the R-Car X5H, is among the first highly integrated multi-domain automotive SoCs built on advanced 3 nm process technology, designed to run ADAS, IVI, gateway, and next-gen SDV workloads on a centralized platform. These platforms deliver high AI performance (e.g., multi-hundreds of TOPS), scalable chiplet-based acceleration, and power efficiency tailored for electrified and autonomous vehicles while meeting stringent functional safety standards. An AI Compiler Engineer enables this hardware vision by ensuring that state-of-the-art AI models and computational kernels are efficiently mapped to the silicon fabric — directly enhancing performance, reducing latency and energy, and accelerating software adoption in automotive ecosystems where compute efficiency and safety are paramount.
【Must-Have】
・MS/PhD (or equivalent experience) in Computer Science, EE, or related field
・Deep experience building AI compilers, accelerator backends, or graph optimization frameworks
・Strong expertise in graph optimization and performance optimization for NPUs or custom accelerators
・Experience with MLIR, LLVM, TVM‑like systems, or proprietary compiler IRs
・Excellent C/C++ and Python skills
・Solid understanding of AI inference workloads (CNNs, transformers, perception or generative models)
・Strong communication skills are required, e.g. agile development experience in Scrum team (Product Owner or Scrum Master)
【Nice-to-Have】
・Experience with automotive or safety‑critical systems
・Background in heterogeneous SoCs (CPU/GPU/DSP/NPU)
・Performance modeling or hardware–software co‑design experience

Work arrangement
No