DFT Engineer

Title: DFT Engineer
(Top20 Semiconductor Organization in the world)
Location: Hyderabad
We are a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. combine analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $10 billion in FY25, we ensure today's innovators stay Ahead of What's Possible.
We are looking for an experienced and hands-on DFT Engineer with strong expertise in Siemens Tessent-based DFT implementation and verification. The role requires solid experience across DFT RTL generation, MBIST, Scan/ATPG, Boundary Scan, timing simulations, and DFT constraints.
Key Responsibilities / Experience
Hands-on experience in DFT RTL generation and integration using Siemens Tessent.
Strong working experience with SSN, SIB, TAP/JTAG, MBIST, and Boundary Scan, including DFT RTL generation and verification.
Hands-on expertise in MBIST RTL simulation and timing simulation, including debugging and validation.
Experience in Scan Stitching, Scan Compression, DFT DRC, and ATPG pattern generation using Tessent.
Generate and validate high-quality manufacturing ATPG patterns for Stuck-at (SAF) and Transition Fault (TDF) models.
Perform validation of DFT structures and patterns at RTL and gate-level/netlist, including simulations with and without SDF.
Develop and validate DFT constraints and work closely with the Physical Design team for synthesis, STA, timing closure, and DFT implementation support.
Hands-on experience with timing simulations and debugging DFT-related timing or pattern failures.
Collaborate with Design, Architecture, Verification, Physical Design, and Product/Test Engineering teams throughout the DFT implementation cycle.
Support debug and resolution of DFT implementation, simulation, coverage, and test-related issues.
Required Skills
Bachelor’s/master’s degree in electrical/Electronic Engineering or a related field.
7–11 years of hands-on DFT experience in ASIC/SoC designs.
Strong hands-on expertise with Siemens Tessent.
Experience with DFT RTL Generation, SSN/SIB/TAP, JTAG, MBIST, Boundary Scan, Scan Stitching, ATPG, DFT DRC, and DFT STA constraints.
Strong experience in MBIST RTL/Timing Simulation and DFT timing simulation.
Good understanding of RTL, netlist, SDF, synthesis, STA, and Physical Design flows.
Scripting experience in Tcl, Perl, and/or Python.
Strong debugging, problem-solving, and communication skills.
CONTACT
SUMIT S. B.
sumit@mulyatech.com
Mulya Technologies
"Mining the Knowledge Community"

Work arrangement
Hybrid