Ethernet System Integration Engineer

Job Details:
Job Description:
Join an enthusiastic team of engineers in Intel's Central Engineering Group (CEG), within the Custom ASICs Development Group (CADG), focused on enabling and integrating the next generation of programmable Infrastructure Processing Units (IPUs) and Foundation Network Interface Card (FNIC) product lines.
As a System Integration Engineer, you will work across the firmware and hardware elements of the 200G/400G/800G/1.6T Ethernet PHY subsystem. Working closely with major cloud service providers and Intel's silicon, hardware, firmware, and software development teams, you will help deliver customized IPU- and FNIC-based solutions that enhance isolation, security, performance, storage, and system management for customers.
This role also includes driving feature-request processes, developing new solutions, and debugging internal and external customer issues.
Responsible for the overall design and development of systems and solutions that integrate software, firmware, board, and silicon/SoC components for a specific segment with specific focus on customer requirements and implementation limitations throughout the systems lifecycle. May also be responsible for systems architecture and definition, including translating the business opportunity into use cases and developing the product specifications for required hardware and software needed to deliver system requirements.
Leads design, analysis, and implementation of component level choices across the integrated systems on performance, features, and cost including technical risk assessment and emphasis on ease of use, reliability, security, availability, maintainability, sustainability, and quality based on system or platform architecture specifications.
Defines systems implementation and integration solutions and plans to ensure optimum performance and reliability across hardware and software that comprise the system. Delivers end-to-end technical solutions to solve customer problems, deploying solutions, executing benchmark tests, and preparing documentation.
Collaborates with other teams to analyze next generation requirements and opportunities and may influence and guide research and academic collaboration on systems and solutions, including proof-of-concept and solutions beyond current industry approaches.
Guides and conducts lab experiments of proof-of-concept innovations and new feature feasibility studies. Simulates real-life environments in the lab and analyzes performance of prototypes.
Responsibilities will include, but are not limited to:
Prepares related installation, operation, and maintenance specifications and instructions.
Execute hands-on tests with lab test equipment to establish operating data.
Responds to customer and client requests or events as they occur.
Develops solutions to problems by applying technical expertise, formal education, and sound judgment.
The ideal candidate will have the following skills in addition to the qualifications listed below:
Strong organizational skills, delivering objectives on schedule and within budget.
A collaborative team mindset.
Strong problem-solving skills.
Excellent communication skills.
Qualifications:
Minimum Qualifications are required to be initially considered for this position.
Bachelor's degree in electrical engineering, computer engineering, computer science, math, physics, or a related field.
2+ years of experience developing SW/FW automated test environments and tools using Python, C, C++, GIT, and shell scripts.
1+ years of experience validating and characterizing IPs in standalone and full-chip environments, including results analysis and debug activities using advanced test and measurement lab equipment, such as oscilloscopes and analyzers, to debug circuit boards.
Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Master's degree or higher.
Experience with high-speed Ethernet PAM4 SerDes.
Familiarity with 802.3 Ethernet Physical Layer technologies
Familiarity with reading and comprehending PCB schematics
Experience in the following fields: RTOS, FW, SW, IO tools, NVM configuration, or Pre-Si verification.
Familiarity with low-speed IO, such as I2C, MDIO, and UART.
Familiarity with Linux.
Familiarity with system software stacks, especially software-hardware interactions across platform firmware, device drivers, the Linux kernel, and user-space application performance.
Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.
Job Type:College Grad
Shift:Shift 1 (United States of America)
Primary Location: US, Oregon, Hillsboro
Additional Locations:
Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/A
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $105,650.00-149,150.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.
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