Physical Design Engineer

Company Description LeadSoC Technologies Pvt Ltd provides cutting-edge engineering design services in VLSI and embedded systems for the semiconductor, automotive, telecom, and consumer electronics industries. Over the past nine years, the company has grown rapidly and delivers end-to-end VLSI design services, from micro-architecture to tape-out and post-silicon support. LeadSoC works on SoC, FPGA, and ASIC platforms across digital front-end, back-end, analog, custom design, RF, and board design, using state-of-the-art tools in its in-house labs to develop and mentor engineering talent. The organization also has a strong software practice covering firmware, platform software, middleware, applications, HMI, IoT, and cloud solutions across multiple architectures and operating systems. Its centers of excellence and lab environments encourage hands-on learning, innovation, and the creation of reference solutions for complex, next-generation products.
Role Description This is a full-time, on-site Physical Design Engineer role based in Bengaluru South. The Physical Design Engineer will be responsible for implementing and optimizing digital designs from RTL to GDSII, including floorplanning, placement, clock tree synthesis, routing, and timing closure. Daily tasks include collaborating with logic and RTL design teams, performing physical verification checks, analyzing power, performance, and area trade-offs, and resolving design and layout issues. The role involves working with industry-standard EDA tools, preparing design documentation, supporting tape-out activities, and contributing to best practices and methodologies within the physical design team. The engineer will also participate in design reviews, coordinate with cross-functional teams, and support post-silicon activities as needed.
Qualifications
Exp- 8+ years
NP- within 30 days
Location- Bangalore
Candidates should possess strong skills in Physical Design, including floorplanning, placement, CTS, routing, and timing closure.
Candidates should possess skills in Physical Verification, including DRC, LVS, EM/IR, and sign-off checks.
Candidates should possess skills in Logic Design and Circuit Design for digital integrated circuits.
Candidates should possess skills in RTL Design, including understanding of HDL (Verilog/VHDL) and synthesis constraints.
Experience with industry-standard EDA tools for implementation and verification (e.g., Cadence, Synopsys, Mentor) is highly beneficial.
Good understanding of CMOS technology, low-power design techniques, and PPA optimization is preferred.
Bachelor’s or Master’s degree in Electrical Engineering, Electronics, VLSI, or a related field is required.
Strong analytical skills, attention to detail, and ability to work collaboratively in on-site, cross-functional teams are expected.

Work arrangement
No