FPGA Engineer IV

Job Details
New ideas are all around us, but only a few will change the world. That’s our focus at JPL. We ask the biggest questions, then search the universe for answers—literally. We build upon ideas that have guided generations, then share our discoveries to inspire generations to come. Your mission—your opportunity—is to seek out the answers that bring us one step closer. If you’re driven to discover, create, and inspire something that lasts a lifetime and beyond, you’re ready for JPL.
Located in Pasadena, California, JPL has a campus-like environment situated on 177 acres in the foothills of the San Gabriel Mountains and offers a work environment unlike any other: we inspire passion, foster innovation, build collaboration, and reward excellence.
Responsibilities:
The JPL Communications and Instruments Division perform scientific investigations, advanced technology research, engineering developments and system implementations encompassing space telecommunications, tracking and active remote sensing using electromagnetic waves.
The Flight Communications and Tracking Section provides cost-effective space communications systems, software defined radios, high power RF amplifiers, and power supplies that support primary telecom subsystems and major radar and radiometer science payloads. The section also provides Global Navigation Satellite System (GNSS) flight equipment, radiometric science instruments, high stability frequency standards and clocks and seismometers for NASA/JPL missions. In addition to flight hardware expertise, the section specializes in collection of and processing of worldwide, fixed site, GNSS data that is processed into clock, atmospheric, and ionospheric GNSS correction metrics. The section also develops high stability frequency references and clocks for flight and ground applications.
The Flight Communications & Tracking Section at JPL is looking for an FPGA Engineer IV to join their Software Defined Radios Group to support FPGA development and implementation for the Polar Rover for Observation, Mapping, and In-Situ Exploration (PROMISE) telecom subsystem. The Group leads the development of software / firmware defined digital flight electronics for telecom, radio metrics, and radar support applications. Work includes development and implementation of flight signal processing algorithms, complex spacecraft interfaces, and various data transfer and communications protocols that enable and support telecom, radar science, instruments, and spacecraft safety and health. Group members work on all phases of product development from early concept, low technology readiness specification and prototyping to engineering and flight model development and implementation, functional and environmental testing, and flight operations support.
PROMISE is a NASA lunar rover mission intended to explore the lunar south pole as part of the Moon Base program. As the PROMISE telecom FPGA Engineer, you will be responsible for the development, implementation, test, and delivery of the flight FPGA firmware for one or several FPGA designs that are part of the Universal Space Transponder (UST) radio family. You will be a member of the multidisciplinary implementation team consisting of approximately 7 full-time equivalent employees, industry partners, and subcontractors. You will report programmatically to the PROMISE Telecom Product Delivery Manager or the PROMISE Radio Cognizant Engineer and administratively to the Group Supervisor of the Software Defined Radios Group.
Tasks may include but are not limited to:
Support telecom system engineering team with FPGA requirements development
Implement signal processing and high-speed data interfaces in the FPGA using Verilog and System Verilog
Implement radiometric processing and telecom waveforms
Implement and validate Spacecraft telemetry modulation, command demodulation, and flight software interfaces
Support radio flight software development and implementation team during FPGA firmware and software integration and testing
Support radio and subsystem integration, test, ATLO, and early operations
Prepare and deliver presentations to technical and management review boards
Provide input to programmatic and technical standards, practices, procedures, processes, and policies
Support or lead flight FPGA implementation, simulation, hardware test, and test data analysis
Develop and maintain comprehensive FPGA documentation, including FPGA development and assurance plan, FPGA configuration management plan, FPGA specification, FPGA requirements, and FPGA test plans and test procedures
Support or lead flight FPGA design and delivery reviews
Generate FPGA End Item Data Package (EIDP) and prepare FPGA flight releases
Qualifications:
BA/BS degree in Electrical Engineering with a minimum of 9 years of related work experience, MA/MS degree in a related discipline with a minimum of 7 years of related work experience, PhD in a related discipline with a minimum of 5 years of related work experience
Experience with complex and large scale FPGA development, such as System on a Chip (SoC) designs
Experience with complex Digital Signal Processing (DSP) implementation and with Spacecraft command, telemetry, and high-speed data interfaces (MIL-STD-1553B, SpaceWire, RS-422, and Ethernet)
Experience with the latest industry FPGA development tools, design flow and verification methodology
Extensive working knowledge with implementing FPGA and ASIC designs using industry standard FPGA development languages Verilog and System Verilog
Extensive knowledge of best industry practices in electronics and FPGA development, implementation, testing, and verification
Experience in the development and delivery of Electra or UST related software defined radio products and space flight hardware
Experience developing design requirements and solving engineering problems
Proven ability to work in a team environment and lead a team of engineers
Ability to meet deadlines and be responsive to customers
Strong communication (oral, written, presentation), interpersonal, negotiation and organizational skills
Advanced knowledge in one or more of the following areas: PWB design, fabrication, and assembly, digital hardware, FPGAs and firmware, microprocessors and embedded software
Familiarity with standard test equipment used for electrical and RF testing
Familiarity with various industry standard scripting languages such as Perl, Python, and TCL
Experience with operating systems Windows, Linux and Bash Shell and Shell scripting
Preferred Skills:
Experience in cost account management and schedule tracking
Advanced knowledge of applicable Laboratory policies and procedures, NASA policies and procedures, and government regulations
Experience with DSP algorithm development, simulation, and analysis
Extensive experience developing, maintaining and managing reusable functional Intellectual Properties (IP’s) for FPGA and Application Specific Integrated Circuits (ASIC’s)
Familiarity with latest industry FPGA/ASIC verification methodologies, such as Open Verification Methodology (OVM) and Universal Verification methodology (UVM)
JPL has a catalog of benefits and perks that span from the traditional to the unique. This includes a variety of health, dental, vision, wellbeing, and retirement plans, paid time off, learning, rideshare, childcare, flexible schedule, parental leave and many more. Our focus is on work-life balance, and living healthy, fulfilling lives as we Dare Mighty Things Together. For benefits eligible positions, benefits are effective the first day of the month coincident with or immediately following the employee’s start date.
For further benefits information click Benefits and Perks
The hiring range displayed below is specifically for those who will work in or reside in the location listed. In extending an offer, Jet Propulsion Laboratory considers factors including, but not limited to, the candidate’s job related skills, experience, knowledge, and relevant education/training.
The typical full time equivalent annual hiring range for this job in Pasadena, California.
$169,520 - $200,824
JPL is an Equal Opportunity Employer. All qualified applicants will receive co