RTL Design -Director(SOC Lead)

This Director-level SoC Lead spans the continuum from high-level system architecture to micro-architectural partitioning and hands-on RTL direction. The mandate spans multi-million gate integration, IP dependency orchestration, synthesis convergence, and timing closure within highly constrained PPA envelopes. At these technology nodes, the architecture is inseparable from the physical reality choices made in topology, buffering strategy, clocking domains, or protocol partitioning, which directly determine feasibility. Only an SoC leader with deep exposure to complex IP optimization and full-chip convergence can prevent costly late-stage refactoring.
You will be part of the CSG team focused on Data Center innovation through next-gen architectures, reshaping compute efficiency and scalability for the AI era .
Define and defend architectural trade-offs
Drive milestone discipline across design, verification, and physical implementation
Assess cross-IP friction
Mentor engineers on design-for-convergence principles
Design knowledge on Ethernet switch and IO chiplet programs are strategically important.
Experience in ultra-high bandwidth data processing space, where low-latency transport, scalable throughput, and energy-efficient data movement are distinct.
Leadership in this space requires someone who has navigated the full design convergence cycle: Architecture → Micro-Architecture → RTL → Verification → Synthesis → Timing Closure.

Work arrangement
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