Low Power Design Engineer

Company Description
Sauvira Solutions Private Limited is a pioneering semiconductor services startup driving India’s semiconductor revolution. The company delivers end-to-end solutions in semiconductor design, verification, and testing that help clients accelerate time-to-market and improve product performance. Its expert engineering teams work on advanced SoC and FPGA design, power and timing optimization, and robust test and diagnosis capabilities. Sauvira Solutions is known for its focus on innovation, customer collaboration, and strict quality standards that ensure reliable, high-performance results. The organization offers a dynamic environment for professionals interested in cutting-edge semiconductor technologies and complex design challenges.
Experience: 3–8 Years
Job Overview
We are looking for a skilled Low Power Design Engineer with experience in ASIC/SoC low-power design methodologies, power intent implementation, and verification. The candidate will work closely with RTL, Physical Design, DFT, and verification teams to implement and validate low-power techniques for complex semiconductor designs.
Key Responsibilities
Develop and implement low-power design methodologies for ASIC/SoC projects.
Work with UPF (Unified Power Format) and CPF (Common Power Format) for power intent specification and implementation.
Define and validate power domains, power states, isolation strategies, level shifters, and retention cells.
Implement power gating, clock gating, and dynamic power reduction techniques.
Perform power intent validation and low-power checks across RTL, synthesis, and physical design stages.
Debug and resolve CLP/VCLP violations and ensure low-power signoff readiness.
Collaborate with RTL, DFT, Physical Design, STA, and SoC integration teams.
Analyze power consumption and identify opportunities for power, performance, and area (PPA) optimization.
Support low-power verification, simulation, and formal checks.
Review power intent specifications and ensure consistency with the design architecture.
Support ECO implementation, debugging, and low-power signoff activities.
Required Skills
Strong understanding of ASIC/SoC design flows and low-power methodologies.
Hands-on experience with UPF/CPF and power intent implementation.
Knowledge of power domains, isolation cells, level shifters, retention strategies, and power state tables.
Experience with power gating, clock gating, and low-power optimization techniques.
Understanding of RTL design, synthesis, and Physical Design flows.
Knowledge of low-power verification and debugging methodologies.
Familiarity with scripting languages such as Tcl, Python, or Shell is an advantage.
Tools
Synopsys: VCS, VC LP, VCLP, Design Compiler, Fusion Compiler.
Cadence: Genus, Innovus, Joules.
Verification: Formality, Conformal LEC.
Scripting: Tcl, Python, Shell.
Preferred Qualifications
B.E./B.Tech/M.E./M.Tech in ECE, EEE, or a related engineering discipline.
Experience with advanced-node ASIC/SoC designs.
Strong debugging, analytical, and problem-solving skills.
Ability to work with cross-functional teams and meet project deadlines.

Work arrangement
No