CTO / Principal RTL Design Architect / Co-founder - AI Accelerator

This is not a standard job post.
We are looking for a co-founder to own the technology side of our NPU: innovation, architecture and implementation, from the first idea to silicon.
What we are building
An AI inference accelerator built from a clean sheet. Two ideas drive the design.
No back and forth of weights. Inference today spends most of its energy and time moving weights between memory and compute. We want an architecture where the weights stay put and the compute comes to them.
Agent context as a first-class tier. Long-running agents hold context for hours. The chip and the memory system have to be designed for that from day one, not for short prompts.
The bar
We are looking for someone who dreams of beating the GPU, Google's TPU, the LPU and Cerebras at inference, not matching them. You know exactly where each one wins and where each one leaves performance on the table, and you have a specific idea of how to do better. If your answer to "why hasn't someone already done this?" is thin, this is not for you.
Challenges you have already tackled
We want to hear about hard problems you have taken on yourself, in areas such as:
DRAM: Have you dealt with DRAM limits head on? Bandwidth walls, capacity, cost and supply shortages. Did you invent a way around them: designs that need less DRAM, keep more on chip, tier memory differently, or make a scarce part go further? DRAM is the constraint that shapes every inference chip today, and we want the person who has already fought it.
Weight and data movement: cutting memory traffic, keeping weights resident, compute-in-memory, near-memory compute, dataflow and tiling choices that changed the numbers.
Power and energy: performance per watt, on-chip memory hierarchy, precision and quantization choices, and where the joules actually go in decode.
Agentic AI workloads: long context, growing KV cache, prefill versus decode, checkpointing and restoring state, and how these change what an inference chip needs.
Silicon delivery: RTL and micro-architecture, verification against a golden model, and the road from proof of concept through FPGA and emulation to tape-out.
Tell us what you measured, what surprised you and what you would do differently. Specifics beat titles.
You
You have a startup founder's mentality. You have built something from nothing, or you are itching to. You make decisions with incomplete information, work with a small team and limited money, and treat constraints as design inputs, not excuses.
You are in the thick of AI, GPUs and neural processing chips, and you have done the homework. You know what is in the market and you think you can do it 10X better.
You have taken RTL and micro-architecture to silicon, or come very close.
You have a view on how LLMs and agents will change what an inference chip needs, and you can defend it against people who disagree.
You are ready to put skin in the game. You are not looking for a job.
You lose sleep over this. That is the reason you are reading this.
What you would own
Architecture and technical roadmap for the NPU, from proof of concept through tape-out.
The build-out of the engineering team and the choice of tools, partners and foundry path.
Compensation, stated plainly
This is equity only. There is no salary until we close external funding, and we will not pretend otherwise. You would be a founding partner with meaningful ownership, on vesting terms agreed up front and put in writing before you commit. Once funding closes, compensation moves to a market-appropriate salary plus your equity. If you need a paycheck from day one, this is not the right fit. If you want to build the chip that defines the company, it is.
How to respond
Send your story, not a résumé alone. Tell us which of the challenges above you have tackled, especially how you handled DRAM, what you think the market gets wrong about inference silicon, and what you would do first.

Work arrangement
Yes