Design For Test Engineer

Company Description Tranzium Semi Private Limited is a growing semiconductor company focused on designing and delivering high-quality integrated circuits and solutions for global markets. The organization emphasizes innovation, reliability, and collaboration across its engineering teams. As part of India’s expanding semiconductor ecosystem, Tranzium Semi offers opportunities to work on cutting-edge design and test methodologies. Team members are encouraged to take ownership, contribute ideas, and develop expertise in advanced semiconductor technologies. The company supports professional growth through challenging projects and a technically driven work environment.
Role Description The Design For Test (DFT) Engineer will be responsible for developing and implementing DFT architectures and strategies for complex ASIC and SoC designs in an on-site role based in Bengaluru. Day-to-day tasks include creating test insertion plans, integrating scan, BIST, and other test structures, generating test patterns, and analyzing coverage and diagnostics. The role involves close collaboration with design, verification, and physical implementation teams to ensure testability, yield improvement, and robust debug capabilities. The DFT Engineer will also support silicon bring-up, test program development, and failure analysis in coordination with manufacturing and test engineering. This is a full-time role requiring hands-on technical execution, documentation, and continuous process improvement in line with project schedules and quality goals.
Qualifications
Strong knowledge of DFT concepts such as scan insertion, boundary scan (JTAG), MBIST, LBIST, and test compression, with experience applying them to ASIC/SoC designs.
Proficiency in digital design fundamentals, RTL (Verilog/SystemVerilog or VHDL), and familiarity with synthesis and timing concepts to ensure test structures are correctly integrated.
Hands-on experience with DFT tools and flows (e.g., Mentor Tessent, Synopsys DFT tools, Cadence DFT solutions) and test pattern generation (ATPG) for stuck-at and transition faults.
Ability to analyze test coverage reports, debug test-related issues, and work with ATE/test engineering teams during silicon validation and production testing.
Solid understanding of semiconductor manufacturing and yield aspects, including methods to improve test efficiency and reduce test cost.
Strong problem-solving skills, attention to detail, and ability to work collaboratively with cross-functional teams in a fast-paced environment.
Effective written and verbal communication skills for documenting DFT methodologies, presenting results, and coordinating with global stakeholders.
Bachelor’s or Master’s degree in Electrical Engineering, Electronics, or a related field; prior experience in DFT or test engineering in the semiconductor industry is highly desirable.

Work arrangement
No