RTL Engineers ( Senior / Lead )

ChipSilica is a specialized Semiconductor engineering services company focused on PCIe and related high-speed interface technologies. The team supports global customers in developing switches, retimers, and SoCs built around PCIe, CXL, UCIe, and other sub-PCIe protocols.
Applicants can expect to work with domain experts on cutting-edge interconnect solutions for next-generation systems. ChipSilica emphasizes deep technical collaboration, high-quality design, and robust product development for complex, performance-critical hardware. For more information about the company and its projects, interested individuals can contact sales@chipsilica.com for sales and careers@chipsilica.com for job opportunities.
Role Description The RTL Engineers (Senior / Lead) will be responsible for architecting, designing, and implementing RTL for PCIe, CXL, UCIe, and related high-speed interface IP and SoCs. Day-to-day tasks include developing micro-architectures, writing synthesizable RTL, performing code reviews, and collaborating closely with verification, physical design, and firmware teams to ensure robust integration. The role involves debugging functional and performance issues, optimizing designs for power, performance, and area, and contributing to design documentation and best practices. Senior and Lead engineers will mentor team members, help define technical direction, and participate in design and schedule planning. This is a full-time, on-site role based in Bengaluru.
Qualifications
Strong skills in RTL design and coding using Verilog/SystemVerilog, with experience in micro-architecture development for complex digital blocks.
Hands-on expertise with PCIe and related protocols (e.g., CXL, UCIe), including link layer, transaction layer, and integration into SoC architectures.
Experience in simulation and functional verification flows, collaborating with DV teams, and using industry-standard EDA tools.
Knowledge of synthesis, timing closure, and design-for-test concepts, working with physical design teams to achieve PPA goals.
Ability to read and interpret protocol specifications, create detailed design documentation, and maintain clean, reusable RTL code.
Strong problem-solving skills, attention to detail, and ability to debug complex design and system-level issues.
Effective communication and collaboration skills, with experience working in cross-functional hardware teams.
Bachelor’s or Master’s degree in Electrical Engineering, Electronics, Computer Engineering, or a related field, with prior experience in ASIC/SoC design.
Prior experience in senior or lead roles, including mentoring, technical ownership of IP blocks, and participation in project planning, is highly beneficial.

Work arrangement
No