Peripherals (Ethernet) Validation Engineer – Staff/ Sr. Lead / Senior Engineer

Company
Qualcomm India Private Limited
Job Area
Engineering Group, Engineering Group > ASICS Engineering
General Summary
As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all. As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional groups to determine product execution path.
Minimum Qualifications
Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
Key Responsibilities
Develop, execute and maintain comprehensive validation plans for Ethernet IP and SoC-level features across pre-silicon, emulation and post-silicon environments.
Collaborate closely with IP architecture, design and systems teams to understand validation requirements and translate them into robust test content.
Lead bring-up, debug and root-cause analysis for complex cross-functional issues spanning hardware, drivers and platform integration.
Ensure validation coverage is sufficient to provide high confidence in functional correctness, performance, power behavior, and production readiness.
Required Skills And Experience
Strong hands-on experience with any of these IPs like Ethernet controllers, NIC architectures, PCIe.
Proficiency in bare-metal and Linux driver development with strong C/C++ programming and debugging skills.
Solid understanding of embedded systems, SoC architecture, peripheral subsystems and hardware/software interaction.
Experience validating complex SoC features across functional, performance, power and system-level scenarios.
Exposure to AI server based interconnects like ESUN/UEC, UALink protocols are preferred.
Hands-on experience with lab and debug tools such as Lauterbach TRACE32, oscilloscopes, protocol analyzers and traffic-generation equipment.
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Work arrangement
No