Senior DFT Engineer

Role: Senior DFT Engineer
Function: Design for Test (DFT) / Semiconductor Engineering
Location: Bangalore / Malaysia / Japan / Chennai
Type: Full-time
Industry: Semiconductors, Information Technology & Services
About Company
A Bangalore-based technology consulting firm specialising in Semiconductor ASIC Design Services and Embedded Software Development. Founded by industry veterans with over 100 years of combined semiconductor experience.
The company guides projects from initial specifications all the way to first-pass silicon success. It operates across six verticals: Design & Verification, Physical Design & SignOff, DFT, FPGA Design, Analog & Analog Layout, and Embedded Software.
A close-knit team of 67, with deep multi-foundry capabilities and advanced node expertise from 180nm to 3nm.
Position Overview
This role sits at the heart of the company's DFT vertical, responsible for defining and implementing test architectures that ensure high fault coverage across complex SoC and ASIC designs. The engineer will own the full DFT flow — from scan insertion and ATPG pattern development through GLS debug and post-silicon bring-up support — working across design, verification, and physical design teams to accelerate client time-to-market.
Role & Responsibilities
Define and implement DFT architecture for SoC/ASIC designs, including scan insertion and scan chain stitching
Develop and validate ATPG patterns for stuck-at, transition, bridge, and path delay fault models
Implement and verify MBIST and memory repair solutions
Perform DFT rule checks (DRC) and drive resolution of violations
Support JTAG/boundary scan (IEEE 1149.1) implementation and verification
Run and debug Gate Level Simulations (GLS) for DFT pattern validation
Analyse and improve test coverage, pattern count, and test time; support post-silicon bring-up and failure analysis
Create and maintain DFT documentation, methodology guides, and best-practice flows
Must Have Criteria
7+ years of hands-on DFT experience on SoC/ASIC designs
Proven experience with scan insertion, scan chain stitching, and ATPG pattern generation (stuck-at, transition, bridge, path delay)
Experience implementing and verifying MBIST and memory repair solutions
Proficiency in DFT rule checks (DRC) and violation debug
Experience with JTAG/boundary scan and IEEE 1149.1 implementation
Hands-on experience running and debugging Gate Level Simulations (GLS) for DFT patterns
Exposure to advanced process nodes and industry-standard EDA tools for DFT
Nice to Have
Experience with post-silicon bring-up and silicon failure analysis
Familiarity with multi-foundry design environments
Exposure to advanced nodes (7nm and below)
Experience authoring DFT methodology documentation and best-practice flows
What We Offer
Opportunity to work on complex SoC/ASIC projects spanning 180nm to 3nm process nodes
Close collaboration with industry veterans carrying 100+ years of combined semiconductor expertise
Skill development through diverse, client-driven semiconductor engagements
Stable, engineering-first culture in a focused 67-person firm

Work arrangement
No