DFT Engineer / GPU Logic Design Engineer

Job Details
Job Description:
The Role and Impact
As a GPU Logic Design Engineer, you will contribute to the design and validation of cutting-edge graphics IPs, including compute, display, and media units. You will be immersed in the creation of register transfer level (RTL) coding, simulation, and optimization strategies to meet power, performance, area, and timing goals. By leveraging your expertise, you will play a pivotal role in enabling high-quality integration of GPU blocks into larger system-on-chip (SoC) designs, directly impacting Intel's future graphics technologies.
Business Group
You will be joining Intel's Data Center Group (DCG), a team dedicated to driving innovation and delivering high-performance solutions for data-centric workloads. The group focuses on developing advanced graphics hardware that powers data center GPU solutions, supporting Intel's broader mission of creating world-changing technology that enriches lives. It offers an exciting environment where collaboration and technical excellence intersect to shape the future of visual computing.
Key Responsibilities
Develop logic design, RTL coding, and simulation for graphics IPs, ensuring compliance with power, performance, area, and timing requirements.
Participate in defining architecture and microarchitecture features for GPU blocks.
Optimize logic design to support physical implementation while maintaining design integrity.
Review and implement verification plans to ensure design features are accurately tested across verification hierarchies.
Drive unit-level verification and resolve RTL test failures to ensure feature correctness.
Support SoC customers in integrating GPU blocks effectively for high-quality results.
Qualifications
Minimum Qualifications
Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field with 3+ years of industry experience, OR a Master's degree in the same fields with 2+ years of industry experience, OR a PhD with no prior professional experience.
Demonstrated expertise in at least one of the following DFT features: TAP/JTAG, Scan/ATPG, or Array DFT (MBIST/PBIST).
Proficiency in EDA tools such as ATPG tools, Mentor Tessent shell, VCS simulation, and debug tools.
Experience in silicon enabling debug or test pattern development.
Preferred Qualifications
Proficiency in design automation and scripting languages for streamlining workflows.
Familiarity with structural design flows, including timing, routing, placement, and clock analysis.
Knowledge of high-volume manufacturing requirements and test flows.
Understanding of 3D, media, and display graphics pipelines.
Awareness of SoC architecture principles and best practices.
Bring your expertise to Intel's GPU Hardware IP team and be a driving force behind the future of graphics and visual computing technology. Collaborate with a diverse and innovative team to deliver impactful solutions that redefine the industry.
Job Type
Experienced Hire
Shift
Shift 1 (India)
Primary Location:
India, Bangalore
Additional Locations:
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

Work arrangement
Hybrid