Analog Layout Engineer

Job Location: Bengaluru, Noida and Hyderabad
Job Description:
Solid experience of 3 to 6 years in developing high speed IO/ESD/Analog layout design.
Expertise in working on FinFet layouts in lower nodes, preference to TSMCN 7nm and below.
Expertise in using the best and latest features of Cadence VXL and Calibre DRC/LVS.
QCT RF/Analog design group is seeking an experienced Layout Engineer to fulfill both block level roles working in a large team environment. Responsibilities will vary depending on experience and expertise. The layout designer will be responsible for physical design of RF and analog circuits in a fast-paced environment. Detail custom layout including floorplan, placement, routing, verification, and release of final database for high frequency RF circuits. Provide accurate schedule and plan to meet project milestone deadlines, debug complex verification errors, mentor junior layout designers, able to lead a team to deliver high quality layout that meets design requirements, understanding of hierarchical planning and integration, chip design from top down and bottom up through Tapeout. The layout designer should have strong analog layout fundamentals and focused exposure to handling multi voltage domain circuit layouts, latchup and ESD aware layout development strategy.
Qualifications
B.E. / B.Tech in Electronics, Electrical, VLSI, or Computer Engineering
M.Tech / M.S. in VLSI, Microelectronics, or related fields (preferred)

Work arrangement
No