Physical Verification

Physical Verification Engineer
Experience: 3-5 Years
Location: Bangalore, India
Employment Type: Full-Time
About Role
We are seeking a highly motivated Physical Verification (PV) Engineer with strong expertise in block-level and full-chip physical verification and signoff. The ideal candidate will have hands-on experience in advanced technology nodes (5nm and below preferred) and a strong understanding of foundry design rules, layout connectivity, and signoff methodologies. In this role, you will own physical verification closure, working closely with physical design and layout teams to deliver clean, foundry-compliant GDS-II for tapeout.
Required Qualifications
Hands-on experience in ASIC physical verification and signoff.
Strong knowledge of DRC, LVS, ERC, antenna rules, metal density checks, and hierarchical verification flows.
Experience with GDS-II/OASIS, layout and netlist debugging, foundry rule decks, and Linux-based verification flows.
Scripting skills in Tcl, Python, Perl, or shell.
Excellent problem-solving and communication skills, with the ability to drive closure independently and collaborate across design teams.
Key Responsibilities
Execute block-level and full-chip physical verification from layout integration through final GDS II signoff.
Run and debug Design Rule Checking (DRC), Layout Versus Schematic (LVS), and Electrical Rule Checking (ERC).
Analyze and resolve shorts, opens, device mismatches, connectivity errors, and power and ground connection issues.
Drive antenna, metal density, and metal fill verification in coordination with physical design and layout teams.
Set up and maintain physical verification flows using foundry-qualified rule decks and approved tool versions.
Manage hierarchical verification, IP integration checks, and top-level physical verification closure.
Use industry-standard tools such as Siemens Calibre, Synopsys IC Validator (ICV), or Cadence Pegasus/PVS.
Share your updated profile to vagdevi@semi-leaf.com

Work arrangement
Hybrid