Digital Design Verification Engineer

We are at a pivotal moment where technology is rapidly evolving, and we have some exciting opportunities within our MCU organization that place us right at the center of this transformation.
Our current work is focused on developing solutions for high-growth markets such as AI-driven data centers and emerging domains like humanoid systems. These areas are shaping the future of computing, automation, and intelligent systems, and offer a unique chance to work on cutting-edge technologies with real-world impact.
If you are passionate about solving complex technical challenges and want to contribute to innovations in these fast-growing segments, I encourage you to come forward and apply. This is an opportunity to be part of a journey that is not only technically rewarding but also strategically significant.
Looking forward to seeing many of you take this step
Minimum requirements:
5 + years of extensive verification experience on high‑performance SoCs, preferably MCUs or wireless connectivity products.
Deep expertise in SystemVerilog/UVM and major simulation platforms; proven track record of delivering high‑coverage verification solutions.
Strong background in power‑aware verification, mixed‑signal (AMS) verification, and hardware emulation (FPGA, Palladium, etc.).
Demonstrated ability to lead coverage‑driven verification campaigns and meet aggressive schedule targets.
Advanced scripting/automation skills (tcl, perl, python, Bash) and familiarity with CI/CD for verification flows.
Excellent communication and stakeholder‑management skills; ability to build strong relationships across functional groups and global sites.
Proven experience mentoring engineers and driving methodology improvements.
Preferred qualifications:
Experience with System Verilog
Demonstrated strong analytical and problem solving skills
Strong verbal and written communication skills
Ability to work in teams and collaborate effectively with people in different functions
Strong time management skills that enable on-time project delivery
Demonstrated ability to build strong, influential relationships
Experience with TI internal verification platforms or custom IP verification frameworks
Publications or conference presentations on verification methodologies.
Hands‑on involvement with silicon bring‑up and debugging on silicon prototypes.
Knowledge of industry standards (IEEE 1800‑UVM, IEEE 1500, IEEE 1149.1) and low‑power verification techniques.