Live opening · Posted 4 days ago
ASIC Design Verification Engineer || Verilog, UVM, Testbench
Cisco · Bengaluru
JobBeeper subscribers received an alert for this role.
Live opening · Posted 4 days ago
The key details from the original listing.
Only a short excerpt is available here.
The full responsibilities and requirements may not be included. Sign in to open the original listing and confirm the details before applying.
Verification,Automation,Software testing,Design engineering,ASIC Verification,Cisco,Case,Test cases
Skills
Verification,Automation,Software testing,Design engineering,ASIC Verification,Cisco,Case,Test cases
Experience
7-12 Yrs
Live timing from JobBeeper.
Recently tracked roles with full details and direct application links.