#STA Engineer

Company Description Mirafra Technologies is a leading provider of turnkey ASIC solutions and semiconductor engineering services, supporting global technology companies from concept to silicon to system. With a team of over 2,200 engineers and delivery centers across India, the United States, Germany, Taiwan, and Malaysia, Mirafra offers a strong global footprint and diverse project opportunities. The company delivers end-to-end expertise across the semiconductor lifecycle, including architecture, design, verification, physical implementation, and system solutions. Mirafra’s track record includes more than 650 tape-out contributions and partnerships with over 50 semiconductor customers, from startups to leading technology enterprises. In addition, Mirafra drives innovation in intelligent embedded products and digital transformation through AI, cloud, data engineering, and scalable software solutions.
Role Description The #STA Engineer will be responsible for performing static timing analysis for complex ASIC and SoC designs, ensuring timing closure across multiple process, voltage, and temperature corners. Day-to-day activities include developing and maintaining timing constraints, analyzing reports, identifying violations, and collaborating closely with RTL design, synthesis, and physical design teams to resolve timing issues. The role involves working with industry-standard STA tools, validating design changes, and contributing to flow and methodology improvements for timing sign-off. This is a full-time, on-site position based in India, offering opportunities to work on cutting-edge semiconductor projects and interact with global engineering teams.
Qualifications
Strong expertise in Static Timing Analysis, including timing constraints (SDC), clock domain management, and timing closure for ASIC/SoC designs.
Hands-on experience with industry-standard STA tools (such as PrimeTime or equivalent) and familiarity with synthesis and place-and-route flows.
Solid understanding of digital design fundamentals, including combinational and sequential logic, clocking, and setup/hold concepts.
Ability to work collaboratively with RTL, physical design, and verification teams to debug and resolve timing-related issues.
Good knowledge of semiconductor process variations, PVT corners, signal integrity, and their impact on timing.
Proficiency in scripting (e.g., Tcl, Python, or shell) to automate STA tasks, reporting, and analysis workflows.
Bachelor’s or Master’s degree in Electrical Engineering, Electronics, VLSI, or a closely related discipline.
Strong analytical skills, attention to detail, and the ability to manage multiple blocks or projects concurrently.
Effective written and verbal communication skills, with the ability to present timing findings and recommendations clearly.
Prior experience in ASIC implementation, sign-off flows, or tape-out environments is highly beneficial.

Work arrangement
No