Logic Design Engineer

Introduction
At IBM Infrastructure & Technology, we design and operate the systems that keep the world running. From high-resiliency mainframes and hybrid cloud platforms to networking, automation, and site reliability. Our teams ensure the performance, security, and scalability that clients and industries depend on every day. Working in Infrastructure & Technology means tackling complex challenges with curiosity and collaboration. You’ll work with diverse technologies and colleagues worldwide to deliver resilient, future-ready solutions that power innovation. With continuous learning, career growth, and a supportive culture, IBM provides the opportunities to build expertise and shape the infrastructure that drives progress.
Your Role And Responsibilities
Your primary responsibilities will include:
Define and document microarchitecture for assigned functional blocks, including pipeline structure, data-path organisation, and control logic.
Author clean, synthesisable RTL in VHDL or SystemVerilog, adhering to team coding guidelines and lint/CDC/RDC cleanliness targets.
Collaborate with architects to evaluate design alternatives and communicate area, power, and frequency trade-offs.
Drive design debug across simulation, emulation, and post-silicon environments; develop debug strategies and root-cause RTL or logic issues efficiently.
Own timing closure for assigned blocks: analyse critical paths, apply SDC constraints, guide ECO strategies, and work with physical design to meet frequency targets.
Review and sign off on verification plans, ensuring functional coverage goals align with the microarchitectural intent.
Participate in design reviews and contribute to cross-project lessons-learned to improve team-wide processes.
Mentor junior engineers on RTL quality, debug methodology, and timing fundamentals.
Preferred Education
Master's Degree
Required Technical And Professional Expertise
5–10 years in digital ASIC or processor logic design, Microarchitecture definition and specification authoring.
RTL coding in SystemVerilog and/or VHDL
Static timing analysis (STA) and SDC constraint authoring
Timing closure — path analysis, ECOs, hold/setup fixing
Design debug: simulation, waveform analysis, emulation
Logic synthesis (Synopsys DC, Cadence Genus, or equivalent)
Lint, CDC, and RDC analysis tools (SpyGlass or equivalent)
Familiarity with formal verification flows
Cross-functional collaboration with physical design and DFT
Preferred Technical And Professional Experience
Experience in high-performance processor, memory subsystem, or high-speed interconnect design (e.g. PCIe, NVLink, OpenCAPI).
Exposure to power analysis and low-power design techniques (clock gating, power domains, UPF/CPF).
Post-silicon bring-up and debug experience including lab instrumentation and JTAG-based debug flows.
Familiarity with emulation platforms (Palladium, Zebu) for pre-silicon debug at speed.
Track record of driving an RTL block from specification to tapeout on a commercial product.

Work arrangement
Hybrid