Engineer – Processor Verification and Compiler Validation

Enphase Energy is a global energy technology company and a leading provider of solar, battery, and electric vehicle charging products. Founded in 2006, our innovative microinverter technology revolutionized solar power, making it a safer, more reliable, and scalable energy source. Today, the Enphase Energy System enables users to make, use, save, and sell their own power. Enphase is also one of the most successful and innovative clean energy companies in the world, with more than 80 million products shipped across 160 countries.
Join our dynamic teams designing and developing next-gen energy technologies and help drive a sustainable future!
About the role
Enphase is looking for a Verification Engineer to help validate a custom RISC-V VLIW processor architecture that powers next-generation digital control systems for energy conversion products. You will be responsible for ensuring deterministic and correct operation across the entire compute stack, including custom hardware pipelines, proprietary instruction set extensions, compiler-generated execution schedules, and closed-loop control applications.
This role is ideal for an engineer who thrives at the intersection of processor architecture, hardware verification, compiler technology, and control systems. You will work closely with architecture, RTL, verification, compiler, firmware, and control algorithm engineers to develop comprehensive verification methodologies that ensure safety-critical control loops execute with predictable timing and flawless functional correctness.
As part of this role, you will also contribute to system-level mixed-signal verification environments that combine RTL simulation, real-number modeling, power stage models, and analog simulation platforms to validate real-world control-loop behavior.
What you will do
Develop and execute verification strategies for a custom RISC-V VLIW processor architecture and associated instruction set extensions.
Create and maintain SystemVerilog-based verification environments, assertions, checkers, scoreboards, coverage models, and regression infrastructure.
Verify pipeline correctness, instruction scheduling behavior, memory subsystem interactions, exception handling, and architectural compliance.
Develop trace-based validation methodologies to ensure deterministic execution timing for real-time control applications.
Analyze execution traces, instruction schedules, waveform data, and performance metrics to identify root causes of hardware or compiler issues.
Collaborate with compiler engineers to validate code generation, instruction scheduling, optimization behavior, and ISA feature utilization.
Drive hardware/software co-verification efforts spanning RTL, compiler toolchains, firmware, and system-level applications.
Contribute to mixed-signal verification environments integrating:
RTL simulation
SystemVerilog Real Number Modeling (RNM)
Analog simulation platforms such as NL5
C/C++ models of power conversion stages and plant models
Python-based analysis and automation frameworks
Validate closed-loop control behavior, timing determinism, fault handling, and system-level interactions between digital control algorithms and analog power stages.
Support verification automation, regression analysis, debug tooling, and continuous improvement of verification methodologies.
Document verification strategies, debug findings, and architectural insights to support long-term product quality and organizational knowledge sharing.
Who you are and what you bring
Bachelor's or Master's degree in electrical engineering, computer engineering, or a related field.
Strong understanding of processor architecture, pipelined microarchitectures, instruction execution, and computer architecture fundamentals.
Experience developing verification environments using SystemVerilog and industry-standard verification methodologies.
Strong debugging and root-cause analysis skills involving complex hardware and software interactions.
Experience analyzing instruction traces, execution timing, and architectural behavior.
Proficiency in Python or similar scripting languages for automation, analysis, and verification infrastructure.
Familiarity with RTL design, simulation, synthesis, and verification workflows.
Strong written and verbal communication skills with the ability to collaborate across architecture, compiler, firmware, and hardware teams.
Demonstrated ability to solve technically challenging problems through data-driven analysis and systematic debugging.
Nice to have attributes
Experience with RISC-V processors and ecosystem tools.