Senior VLSI Design Engineer

Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape.
Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality.
Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward.
Description
Job responsibilities:
- 4-7 Years of relevant experience
Able to lead and Develop test plans, tests and verification infrastructure for a complex IP/sub-modules
Create verification environment using UVM methodology
Create reusable bus functional models, monitors, checkers and scoreboards
Drive functional coverage-driven verification closure
Work with architects, designers, and post-silicon teams
Hands-on contributions to SVA development like coding, porting and maintaining System Verilog Assertions
Debug failures and root-cause it by interacting with other teams/groups Etc.
Skills Required/Preferred
Software Skills Required:
Proficiency in Computer Science fundamentals – object-oriented design
Basic knowledge of with c, c++, perl, python, tcl, shell is preferable
Functional Verification:
Unit/Sub-modules/Full chip IP verification experience
Experience in verification closure of complex IP for at least one project
Exposure to industry standard verification tools for simulation and debug
Exposure to end-to-end verification workflows starting from Verification planning to Sign-off
RTL & Formal / Zero-delay Netlist Verification
Proficiency in Verilog, System Verilog & Assertions
Exposure to AI-ML Verification practices
Verification Automation using scripts like Perl, Shell, TCL
Good debugging and problem-solving skills
Good communication skills and ability, desire to work as a team player
Exposure to Analog-on-Top Design-Under-Test Verification will be additional plus point
Digital design Concepts
CMOS VLSI, Digital Circuits
Knowledge on Memory (preferred)
(NAND Flash/SRAM/DRAM/ROM) Circuits/Logic
Preferred exposure
Xcelium, IMC, Verdi, Jasper, Verisium Manager, VS Formal
RNM / VAMS Modeling Verification
Verification to Design-Under-Test containing Netlist, RTL & C-based Model
Education:
B.E/B.Tech/M.Tech in ECE/VLSI/Electrical Engineering
Additional Information
Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution.
Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at jobs.accommodations@sandisk.com to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying.

Work arrangement
No