Principal Engineer -Validation

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Job Description:
About the Role
You will validate features of Microchip SoC/FPGA products. The role needs deep analytical reasoning to find root causes of system-level failures found during validation. You will also lead a group of junior engineers.
Primary Responsibilities
Validate Programming, Security (crypto) and Debug features on pre-silicon, emulation and post-silicon platforms.
Write system-level and product-level validation plans, use-case (UC) plans and coverage plans. Execute them, then record and communicate results.
Create system and FPGA designs that exercise each product's use models and mimic customer applications.
Bring up FPGA prototyping and emulation platforms. Write and execute emulation plans from the specifications.
Review firmware and architecture specifications. Identify gaps and drive fixes with the owners.
Write and maintain Verilog/VHDL and embedded C/C++ code (ARM/RISC-V).
Build and maintain regression frameworks in TCL (Libero), Python and shell on Linux and Windows. These cover design regeneration, IP-version migration, SDC handling, failure analysis, reporting and notification.
Validate Microchip tool flows (Libero synthesis, place-and-route, IP catalog and versioning).
Debug on hardware using on-chip debug tools, JTAG/FlashPro, SoftConsole and lab equipment.
Assign and manage work, mentor engineers, and work with design, firmware, IP, software and architecture teams.
Requirements/Qualifications:
Qualifications / Requirements:
BSEE/MSEE or equivalent, with 8+ years of silicon or FPGA validation experience.
Excellent verbal and written English communication.
Strong Verilog/VHDL RTL skills, and simulation and synthesis flows (ModelSim/QuestaSim, Synplify or equivalent, Libero).
Strong understanding of hardware and system-level IC architectures, end-use scenarios and FPGA architecture.
Working knowledge of embedded processors (ARM Cortex-M, RISC-V) and AMBA protocols (APB, AHB, AXI). Embedded C/C++ experience.
Strong background in FPGA prototyping and emulation, silicon validation, failure analysis and debug.
Scripting proficiency in TCL and Python.
Board-level lab debug skills: oscilloscopes, logic and protocol analyzers, and integrated logic analyzers (Identify, ChipScope, SignalTap). Knowledge of SPI, I2C, UART, USB and JTAG.
Expertise validating NIST-compliant security on post-silicon: ECC/ECDH, AES, SHA, key provisioning, certificates, protection and authentication. PQC experience is a plus.
Experience leading a group of engineers.
Commitment to quality, ownership and customer satisfaction.
Preferred
Experience with PolarFire / PolarFire SoC / RT PolarFire or similar FPGA families.
Experience with JIRA, Artifactory, Confluence, Git and CI/regression dashboards.
Experience with Corelis/JTAG-based test platforms.
Travel Time:
25% - 50%
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