Senior Staff Engineer - AMS Layout

Job Summary**
We are seeking a highly skilled and experienced Senior Staff Engineer - AMS Layout to join our team. In this role, you will be responsible for leading and executing the physical layout of complex Analog/Mixed-Signal (AMS) integrated circuits, ensuring performance, reliability, and manufacturability for cutting-edge semiconductor designs.
Job Responsibilities**
* Lead and perform the physical layout design of highly complex Analog/Mixed-Signal (AMS) blocks and full chips, including custom circuits, RF, power management, and high-speed interfaces.
* Collaborate closely with design engineers to understand circuit requirements, identify layout challenges, and propose optimal layout solutions.
* Perform floor planning, block-level layout, and top-level integration, ensuring efficient utilization of silicon area and adherence to design specifications.
* Conduct comprehensive physical verification (DRC, LVS, DFM, ERC) using industry-standard tools and resolve identified issues.
* Must have exposure of solving critical latchup, Antenna and density related fixes.
* Perform parasitic extraction and back-annotation for post-layout simulations, working with design teams to ensure performance targets are met.
* Develop and implement innovative layout techniques to optimize performance, power, and area for critical AMS circuits.
* Mentor and provide technical guidance to junior layout engineers, fostering a collaborative and knowledge-sharing environment.
* Contribute to the development and improvement of layout methodologies, best practices, and automation scripts.
* Participate in design reviews and provide constructive feedback to ensure high-quality layout delivery.
* Interface with foundry representatives to understand process rules and ensure designs are compliant with manufacturing requirements.
Job Qualifications**
* Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or a related field.
* 10+ years of hands-on experience in Analog/Mixed-Signal (AMS) IC layout design.
* Expert proficiency in using industry-standard EDA tools such as Cadence Virtuoso Layout Suite (XL), Mentor Graphics Calibre, Synopsys IC Compiler II.
* Deep understanding of semiconductor physics, fabrication processes, and their impact on layout design.
* Extensive experience with various AMS layouts, including ADCs, DACs, PLLs, LDOs, Op-amps, high-speed interfaces, and RF blocks.
* Solid knowledge of deep submicron process technologies (e.g., 28nm, 16nm, 7nm, 5nm).
* Strong understanding of layout effects on circuit performance (e.g., matching, coupling, IR drop, electro-migration, latch-up).
* Experience with scripting languages like Perl, Python, or Skill for layout automation is highly desirable.
* Excellent problem-solving, analytical, and communication skills.
* Ability to work independently and as part of a multi-disciplinary team in a fast-paced environment.
* Prior experience in a leadership or mentorship role is a plus.

Work arrangement
No