OPC Technology Transfer Engineer (R&D)

About TI
Texas Instruments Incorporated (TI) is a global semiconductor design and manufacturing company that develops analog ICs and embedded processors. By employing the world’s brightest minds, TI creates innovations that shape the future of technology. TI is helping about 100,000 customers transform the future, today. We’re committed to building a better future – from the responsible manufacturing of our semiconductors, to caring for our employees, to giving back inside our communities and developing great minds. Put your talent to work with us – change the world, love your job!
About the job
As a Senior OPC Technology Transfer Engineer within the Advanced Technology Development (ATD) organization, you will bridge the gap between initial R&D development and High-Volume Manufacturing (HVM) by owning the full lifecycle of transferring developed OPC technologies to production Fabs. In this role, you will thoroughly analyze process, equipment, layout, and tool disparities between R&D and HVM environments to proactively predict, mitigate, and resolve transfer risks prior to recipe release, ensuring a seamless, high-yield production ramp-up. You will utilize your deep technical knowledge of core semiconductor processes—specifically Photolithography and Etching—to align transferred OPC solutions with production-line physics and hardware characteristics. Serving as a technical leader crossing organizational boundaries, you will partner closely with manufacturing operators, shift technicians, and Fab staff to coordinate test wafer execution, align expectations, and drive collaborative alignment. Additionally, you will leverage data science methodologies to collect, analyze, and interpret large-scale wafer measurement datasets to evaluate OPC recipe performance for final manufacturing sign-off, while compiling and analyzing high-volume SEM images and Critical Dimension (CD) data to verify R&D software model behavior against physical production silicon. Finally, you will analyze automated OPC verification results to identify lithographic critical care-abouts and strategically select key metrology targets for systematic layout review and CD-SEM measurement tracking.
Minimum requirements:
Masters in Electrical Engineering, Physics, Computer Science, Chemistry or related degree
5+ years experience in a semiconductor photolithography and/or OPC development
Lithography & RET expertise for 45nm, 28nm, 22nm or 20nm processing nodes
Hands-on experience handling high-volume SEM measurement data and image inspections
Strong layout review skills using OPC verification tools to determine and isolate critical metrology targets
Profound understanding of OPC development flows, process window optimization, and design rule constraints
Preferred qualifications:
Strong knowledge/understanding of advanced lithography processes, lithography simulation techniques, mask making and RET techniques used in semiconductor manufacturing and process development
Demonstrated leadership skills with the ability to influence cross-functional teams and effectively communicate technical requirements to manufacturing staff on the Fab floor
Familiarity with physical layout (gds/oas). Knowledge of litho/OPC test pattern design and layout execution using test pattern generators and use of layout software like Virtuoso, KLayout
Programming experience in Unix environment
Understanding of OPC pattern validation methodologies and process window assessment techniques like KLA’s Photolithography Wafer Qualification (PWQ)
Demonstrated strong analytical and problem solving skills
Strong verbal and written communication skills
Ability to work in teams and collaborate effectively with people in different functions
Strong time management skills that enable on-time project delivery
Demonstrated ability to build strong, influential relationships
Ability to work effectively in a fast-paced and rapidly changing environment
Ability to take the initiative and drive for results