Principal Digital Design Engineer

About Analog Devices
Analog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.
Description:
The Digital IP team within Analog Devices Inc. is responsible for developing, curating, and providing reusable strategic IPs to Business Units to accelerate product development across the company. The team is looking for an experienced Digital Design Lead who will be responsible for providing technical leadership to the digital design team, while managing IP development and delivery.
The ideal candidate would be someone with strong technical background combined with management acumen and demonstrable ability to handle ambiguity while still finding creative ways to make things happen.
A key focus area for this position includes interacting and engaging with internal customers to communicate, identify, improve, and maintain developed IP, as well as scout for 3rd party IPs and evaluate them on a regular basis for future requirements.
Job Responsibilities:
Provide technical leadership and expertise to a team of design engineers on all aspects of digital design & quality assurance (CDC, Low Power design, Synthesis & timing closure, Design for Test improvements, silicon debug etc)
Architect and Design key digital blocks such as accelerators/ data path IP in Verilog/ System Verilog with built-in configurability to allow Power/ Performance/ Area tradeoffs
Demonstrate strong understanding of heterogenous processor cores & subsystems (A55/ M55/ M4/ U55/ RISC-V/ DSP core, and associated infrastructure such as caches, interconnect fabric, GIC, DMA, MMU, Coresight Debug & Trace, TZC, SMPU, SPU) and their integration requirements
Work closely with all stakeholders, including product teams, project managers, senior managers & leadership team to align team schedules, milestones, commitments, deliverables
Conduct detail-oriented design reviews and drive adherence to quality metrics
Create and manage a streamlined workflow for the design team that enables them to work collaboratively and efficiently. This includes creating a project visibility system and setting up design review processes to establish a clear scheme of design delivery
Drive efforts towards development of Design Management and IP Centric infrastructure and flows across different tools such as Methodics / Perforce / Github / IP catalog creation etc
Develop and maintain catalog of digital IPs to enable ease of information sharing to customers across different BUs
Lead the way to build deep expertise on complex interfaces, peripherals & protocols such as DDR, Ethernet, eMMC/ SD, MIPI, Display Port, HDMI, PCIe, high speed D2D
Package Digital IP for seamless integration into design flow at different stages – RTL/ constraints/ CDC waivers, timing wavers, DFT DRCs and waivers, software programming sequence etc.
Drive evaluation of 3rd party IPs on Power/ Performance/ Area (PPA) and other key qualitative aspects such as design quality, Design For Testability, robustness of Design Verification (DV) practice, ease of integration and make recommendations
Establish evaluation flows for home-grown & 3rd party IPs for consistent benchmarking of evaluation
Manage & streamline efforts towards consolidation/ curation of digital IP blocks, such as standard peripherals, processor cores & collaterals, high speed protocol & interface IP
Strive to remove complexity and ambiguity within the teams and their processes. Ability to distil and provide clear and actionable recommendations to the team
Position Requirements:
Minimum B.E. /B. Tech degree in Electrical/Electronics/Computer science
15+ years of relevant experience with a strong focus on definition/ architecture/ u-arch/ design and hands-on RTL coding experience using Verilog and System-Verilog
Strong understanding of all aspects of ASIC/SoC product development incl Design Verification/ timing constraints/ closure, physical implementation, quality assurance flows with hands-on prior experience in a few of these aspects
Proven experience in managing/ handling large complex hardware projects in lead role
Strong understanding of control path and data-path digital design concepts with an eye for realizing correct by construction solutions
Experience with specifying Design Verification (DV) requirements such as test plans, coverage metrics, and evaluate DV quality so as to realize robust design quality
Strong knowledge of Lint, CDC, formal equivalence, DFT concepts, power analysis, low power design
Experience with developing timing constraints and ability to carry out logic synthesis and Static timing analysis
Ability to technically mentor a large digital design team
Good interpersonal, teamwork and communication skills to drive discussions logically & effectively with teams spread geographically
Strong understanding of standard on-chip interfaces such as APB/AHB/AXI/ Stream protocols
Knowledge of Processor/SoC architecture and/or DSP fundamentals
Serve as the focal point for communications. Compile regular status updates for all stakeholders and effectively escalate critical issues and risks as necessary
For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.
Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.
Job Req Type: Experienced
Required Travel: Yes, 10% of the time
Shift Type: 1st Shift/Days