Staff ASIC Validation Engineer

Family Description
Applied R&D (AR) consists of target-oriented research either with the goal of solving a particular problem / answering a specific question or for multi-discipline design, development, and implementation of hardware, software, and systems including maintenance support. Supplies techno-economic consulting to clients. AR work is characterised by its detailed and complex nature in order to systematically combine existing knowledge and practices to further developing and incrementally improving products, operational processes, and customer-specific feature development.
Subfamily Description
Digital Hardware (DHA) comprises the specification, design, and implementation of digital hardware (baseband hardware) while applying design targets such as low cost, high yield, and high reliability. Digital boards are high density boards with numerous components including high speed connections and high precision reference clocks. DHA requires analogue design knowhow and simulation capabilities.
Bachelor's in Electrical Engineering or Computer Engineering.
10+ Years of work experience in verification and Lab validation of ASICs.
Proficiency in scripting languages: Python preferred.
Experience in leading a small team for technical work.
Familiarity with the Traffic generator.
Familiarity with Ethernet and OTN standards.
Working as independent contributor in development of the ASIC validation & characterization plan.
Development of validation tests on ZeBu emulator prior to ASIC proto arrival.
Validation environment updates and automation where possible.
Working with design & verification team to review test scenarios and debug support.
Supporting HW/SW bring-up and debug.
Working with the x-functional teams to debug any issues at the product level.

Work arrangement
Hybrid