SoC Physical Design Engineer

You will work on physical design implementation of Optical Network ASICs and will be learning latest technology nodes and developing flow, doing implementation to achieve best in class ASICs, which are optimized for power, performance and area metrics.
NION2026
3+ years of experience in ASIC physical design flow and methodologies in 3/5 and 7nm process nodes
Has solid knowledge of full design cycle from RTL to GDSII and understanding of underlaying concepts of IC design, implementation flows and methodologies for deep submicron design
Experience with EDA Place & Route tools like Fusion Compiler or Innovus or similar tools and Timing tools like Primetime or similar, PV tools like Calibre and IR tools like Redhawk
Scripting experience in TCL, python or Perl
Candidates must have a bachelor's degree or higher in Electrical/Electronics and Communication/VLSI/Microelectronics with very good academics
Perform physical implementation steps including floor planning, place and route, power/clock distribution, physical verification and timing closure at block level as well as full chip
Work with logic designers & Hardware team to drive feasibility studies and explore design trade-off for physical design closure
Perform technical evaluations of IP vendors, process nodes and provide recommendations
Develop physical design methodologies and automation scripts for various implementation steps from Synthesis to GDSII
Perform static timing analysis, create timing constraints and validation, critical path analysis, timing closure and timing sign-off
Perform Physical verification and IR/EM analysis on blocks as well as top

Work arrangement
Hybrid