Live opening · Posted 3 days ago

GPU IP Integration Model Build Engineer

Intel · Bengaluru, Karnataka, India (On-site)
Linkedin No
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At a glance

The key details from the original listing.

Posted 3 days ago
CompanyIntel
LocationBengaluru, Karnataka, India (On-site)
Work modeNo
SkillsPython
SourceLinkedin
ListedPosted 3 days ago

About the role

Description supplied by the original job listing.

Job Details
Job Description:
Performs functional verification model integration of graphics logic components, including 3D graphics, media, to ensure design will meet specification requirements. Participates in the definition of verification infrastructure and related TFMs needed for functional design verification. Closely work with different clusters owners and integrate their code into media IP.
Qualifications
Minimum Qualifications:
Master's degree in a relevant field (e.g., Electronics, Computer Science, Embedded Systems) with 3-7 years of hands-on experience in domain-specific areas such as pre- silicon simulation model builds, VLSI design, or testing.
Ability to design, develop, understand, and optimize test environments such as stress stimuli and trackers to validate and verify products, components, and systems.
Ability to architect and implement an IP test environment (checkers, monitors, test infrastructure, VC) to meet the requirements of IP/SoC including expertise in Verdi, VCS, and UVM/OVM
Knowledge of digital basic building blocks (including combinatorial/sequential design, finite state machines, registers, counters),
Ability to make commitments through clear, prioritized goals and high-quality decisions, assume responsibility for outcomes, and predictably execute and meet those commitments over time. Ability to overcome challenges, recover from setbacks, and adapt and adjust course as needed based on data to achieve desired results for the team, customers, and Intel. Consistently uses Intel's enterprise standards for goal setting, decision making, and meeting practices to move work forward rapidly and effectively.
Knowledge of tools and flows used to validate an IP and handoff to SoC.
Ability to identify and diagnose a problem, to propose, implement, and test solutions, and to drive effective and sustainable solutions across unique situations.
Knowledge of validation processes including HSD-ES, DCCB (APM), and Gatekeeper management.
Working knowledge of scripting languages, including Python, Perl, or Ruby.
Demonstrated problem-solving, debugging, and technical analysis skills.
Preferred Qualifications
Understanding of media industry trends and technologies.
Strong communication and teamwork skills to drive collaboration across technical teams.
Take the next step in your career by joining Intel's team of experts dedicated to pushing the boundaries of technology. Your contributions will help shape the future of computing, and we look forward to exploring your unique perspective and skills.
Job Type
Experienced Hire
Shift
Shift 1 (India)
Primary Location:
India, Bangalore
Additional Locations:
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Work Model for this Role
This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

Work arrangement
No

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