Frontend Design / Timing Constraints Lead

OUR STORY
At STMicroelectronics, we believe in the power of technology to drive innovation and make a positive impact on people, businesses, and society. As a global semiconductor company, our advanced technologies and chips form the hidden foundation of the world we live in today.
When you join ST, you will be part of a global business with more than 115 nationalities, present in 40 countries, and comprising over 50,000 diverse and dedicated creators and makers of technology around the world.
Developing technologies takes more than talent: it takes amazing people who understand collaboration and respect. People with passion and the desire to disrupt the status quo, drive innovation, and unlock their own potential.
Embark on a journey with us, where you can innovate for a future that we want to make smarter and greener, in a responsible and sustainable way. Our technology starts with you.
YOUR ROLE
We are seeking a skilled and motivated SoC Timing Constraints Lead with a minimum of 10–14 years of relevant experience to join our team. The ideal candidate will have strong expertise in digital circuit design, timing constraints, SoC IO protocols, timing analysis, constraints verification, and implementation using industry-standard EDA tools. You will work closely with cross-functional teams to develop digital IP-level and SoC constraints, ensuring constraints sanity, constraints verification, and timing closure.
Your Skills & Experiences
10+ years of experience in SoC timing constraints, STA, and digital design.
Strong prior exposure to the SoC timing constraints domain, including constraint promotion/demotion, SoC interface constraints, and their validation.
Exposure on Agentic AI for constraints development.
Expert in SoC IO constraints and design expert in SoC IO protocols.
Ability to define and apply timing constraints to meet performance and power targets.
Experience performing Static Timing Analysis (STA) and debugging timing violations.
Collaboration with synthesis, place & route, and verification teams to achieve design closure.
Ability to optimize designs for area, power, and timing.
Participation in design reviews and contribution to technical documentation.
Support for integration and bring-up activities of digital blocks on silicon.
ST is proud to be one of the 17 companies certified as a 2025 Global Top Employer and the first and only semiconductor company to achieve this distinction. ST was recognized in this ranking thanks to its continuous improvement approach and stands out particularly in the areas of ethics & integrity, purpose & values, organization & change, business strategy, and performance.
At ST, we endeavor to foster a diverse and inclusive workplace, and we do not tolerate discrimination. We aim to recruit and retain a diverse workforce that reflects the societies around us. We strive for equity in career development, career opportunities, and equal remuneration. We encourage candidates who may not meet every single requirement to apply, as we appreciate diverse perspectives and provide opportunities for growth and learning. Diversity, equity, and inclusion (DEI) is woven into our company culture.
To discover more, visit st.com/careers.

Work arrangement
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