Live opening · Posted 6 hours ago

Design Verification Engineer | BGP

Texas Instruments · Dallas, TX, United States
Oracle
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At a glance

The key details from the original listing.

Posted 6 hours ago
CompanyTexas Instruments
LocationDallas, TX, United States
SkillsPython
SourceOracle
ListedPosted 6 hours ago

About the role

Description supplied by the original job listing.

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Texas Instruments is seeking Design Verification Engineer. In this role you will confirm the accuracy of designs for analog and mixed signal electronic parts, components, or integrated circuitry for analog and mixed signal electronic equipment and other hardware systems before pattern generation/mask development. The role will require working independently from the product development team who designed the devices to confirm adherence to known design rules, procedures, and best practices. Additional job functions include analyzing equipment to establish operating data and conducting experimental tests and evaluating results to confirm the device meets all requirements in the specifications. You may also run software simulations, selecting components and equipment based on analysis of specifications and reliability.
As a Design Verification Engineer, you will work across the full verification cycle – from developing detailed verification plans and building test benches through running coverage regressions, tracking closure and contributing to continuous improvements in DV methodology. You will collaborate closely with digital design, analog design and systems engineering teams.
Minimum requirements:
Bachelor’s degree in Electrical Engineering, Electrical and Computer Engineering, Computer Engineering or related field
3+ years of experience in design verification or a related role
Preferred qualifications:
Experience with functional verification methodologies including simulation, assertions, and coverage-driven verification
Proficiency in SystemVerilog and UVM-based testbench development
Familiarity with RTL simulation tools (Cadence Xcelium, Synopsys VCS, or equivalent)
Experience with gate-level simulation and timing-aware verification flows
Scripting skills for regression automation and verification flow development (Python, Tcl, or Perl)
Ability to quickly ramp on new systems and processes
Ability to take the initiative and drive for results
Ability to establish strong relationships with key stakeholders critical to success, both internally and externally
Strong verbal and written communication skills
Demonstrated strong interpersonal, analytical and problem-solving skills
Ability to work in teams and collaborate effectively with people in different functions
Strong time management skills that enable on-time project delivery

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