Live opening · Posted 23 hours ago

VLSI Physical Design & STA Faculty (Part-Time)

PhysicsWallah · Noida, Uttar Pradesh, India (Remote)
Linkedin Yes 3+ yrs
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At a glance

The key details from the original listing.

Posted 23 hours ago
CompanyPhysicsWallah
LocationNoida, Uttar Pradesh, India (Remote)
Experience3+ yrs
Work modeYes
SkillsVLSI, Linux
SourceLinkedin
ListedPosted 23 hours ago

About the role

Description supplied by the original job listing.

Job Description – Part-Time VLSI Physical Design & STA Trainer
Organization: Physics Wallah (PW)
Job Type: Part-Time
Work Mode: Online
About the Role
Physics Wallah (PW) is looking for an experienced VLSI Backend Faculty / Trainer to train freshers for placement opportunities in Physical Design and Static Timing Analysis (STA). The ideal candidate should have strong hands-on industry experience, expertise in Synopsys tools, and the ability to explain complex technical concepts through practical examples and real-world design flows.
Key Responsibilities
Teach VLSI Physical Design, Static Timing Analysis (STA), and physical verification concepts in a structured, easy-to-understand manner.
Conduct hands-on lab sessions using Synopsys tools and industry-relevant design flows and scripts.
Develop and update course curriculum, presentations, lab exercises, assignments, and quizzes based on current industry requirements.
Guide students through backend design projects and practical implementation exercises.
Conduct mock interviews and prepare students for VLSI backend placement opportunities.
Conduct regular doubt-clearing sessions and monitor student progress.
Collaborate with the team to enhance learning outcomes and improve student placement readiness.
Required Skills & Experience
Minimum 3 years of hands-on experience in VLSI Backend / Physical Design.
Strong understanding of the complete RTL-to-GDSII flow, including synthesis, floorplanning, power planning, placement, Clock Tree Synthesis (CTS), routing, timing ECO, and signoff.
Proficiency in Synopsys tools: Fusion Compiler (FC), PrimeTime (PT), Design Compiler (DC), ICC2, StarRC, and IC Validator (ICV).
Knowledge of Calibre for DRC/LVS is an added advantage.
Strong understanding of STA, setup and hold fixing, OCV/AOCV, crosstalk, IR drop, electromigration (EM), and low-power design using UPF.
Good TCL scripting and Linux skills.
Experience with tapeout at 28nm or below is preferred.
Excellent communication skills in English and Hindi.
Ability to explain technical concepts clearly and train freshers for industry requirements.
Preferred Candidate Profile
Working professionals with relevant VLSI industry experience.
Candidates with practical exposure to Physical Design, STA, and signoff activities.
Professionals interested in part-time teaching, mentoring, and placement-oriented training.
Why Join PW?
Opportunity to share industry expertise with aspiring VLSI professionals.
Contribute to practical, industry-aligned learning and placement preparation.
Be part of a growing technical education initiative.
Interested candidates can apply by sharing their updated resume and relevant industry experience.

Skills
VLSI, Linux

Experience
3+ yrs

Work arrangement
Yes

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