Senior ASIC Validation Engineer

##
Company:
Qualcomm India Private Limited
## Job Area:
Engineering Group, Engineering Group > ASICS Engineering
General Summary:
Job Description
Strong programming skills in C and C++ for resource-constrained systems
Proficent in Python programming
Excellent knowledge in low level firmware/ baremetal HW/IP driver writing.
Root-cause analysis of silicon failures abd Hardware debug and failure isolation
Performance characterization and Power and thermal validation
Indepth understand of the HW is must
Should have exposure to Hardware initialization, Validation diagnostics development and firmware optimisations
Good knowledge of how to use embedded development tools such as JTAG and associated debug tools
Work experience on ARM Cortex platform/ MIPS/RISC-V cpus.
Work Experience with FPGAs based platforms is plus
Should have good knowledge of System software stack, Power Management, High speed peripherals, USB, SDIO,Ethernet,PCIe etc and memory subsystem like DDR/LPDDR etc.
Exposure to PCIe Gen4/Gen5/Gen6,25G/50G/100G/200G/400G Ethernet,CXL,DDR4/DDR5/LPDDR,SerDes,UCIe interface validation
Familiarity with software configuration management tools, defect tracking tools, and peer review.
Work Experience with FPGAs based platforms is plus
Work experience on Heterogeneous and Multiprocessor SoC platforms.
Exposure to Pre-Silicon environment with RTL Co-Simulations is plus point
Experience with development environments such as Linux, Git, Jira and Confluence
Strong communication skills to exchange ideas and work as a team
Responsibilities
Develop low-level drivers, bootloaders, BSPs, middleware, and application firmware.
Work closely with hardware,RTL and DV engineers to develop and debug.
Lead post-silicon bring-up and validation of given module of ASIC/SoC products.
Drive debug and root-cause analysis of silicon, firmware, and system-level issues.
Develop firmware and low-level software required for silicon bring-up, subsystem enablement, and debug.
Debug complex hardware-software integration issues using oscilloscopes, logic analyzers, protocol analyzers, JTAG/SWD debuggers, and other laboratory equipment.
Analyze protocol traces, link training behavior, LTSSM states, error logs, and performance bottlenecks.
Develop production-quality software, including testing, documentation, static analysis, and CI/CD/CT
Develop Python-based automation frameworks for validation and regression testing.
Interacting with hardware, software and other teams to validate SoCs with minimum delays
Minimum Qualifications:
• Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field.
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Skills
Python, C++, Git, Linux, CI/CD, Jira, Confluence, Documentation

Experience
2+ yrs

Work arrangement
onsite