Public listing
Principal ASIC Design Engineer (1161503)
- Salary401(k) benefit
- Experience8+ yrs
- Work modeYes
- ListedPosted 8 days ago
- SourceLinkedin
Role overview
About the role
Description supplied by the original job listing.
Location: St Paul, MN, USA
Salary: $190,000.00 USD Annually - $220,000.00 USD Annually
Description
Title: Principal ASIC Design Engineer
Type: Full time
Location: Remote with onsite travel once a month
We are seeking a Principal ASIC Design Engineer to lead the architecture, design, implementation, and validation of advanced ASIC and FPGA solutions for complex, high-performance products. This role will be responsible for planning and developing digital systems and subsystems while collaborating with architecture, verification, analog, physical design, and systems engineering teams throughout the product lifecycle.
Key Responsibilities
Lead the design and development of complex digital systems, subsystems, and design blocks for ASIC and FPGA implementations.
Partner with architects to define requirements, functionality, and system-level specifications for digital designs.
Collaborate with systems, architecture, and analog engineering teams to define and document digital and analog interfaces and interactions.
Develop detailed design specifications, implementation plans, and technical documentation for digital systems.
Create, maintain, and optimize Register Transfer Level (RTL) code using industry-standard hardware description languages.
Develop test strategies and work closely with Design Verification teams to ensure complete functional verification of digital designs.
Perform RTL synthesis using industry-standard EDA tools and analyze results to achieve design objectives.
Optimize designs to meet power, performance, and area (PPA) targets.
Lead post-silicon validation activities at the system and subsystem levels, including developing and executing validation plans.
Support digital systems throughout productization, manufacturing, and production phases.
Develop and maintain process automation and design methodology tools using scripting languages such as Python, Perl, and Tcl.
Provide technical leadership, mentorship, and guidance across engineering and design teams.
Required Qualifications
Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field. Master's degree preferred.
Significant experience serving in a Principal ASIC Design Engineer or equivalent senior-level design role.
Strong experience with ASIC and FPGA design methodologies and development flows.
Proficiency in RTL design using industry-standard hardware description languages such as Verilog, SystemVerilog, or VHDL.
Experience with synthesis, linting, and clock domain crossing (CDC) analysis tools.
Experience developing and supporting embedded digital systems and subsystems.
Proficiency with scripting languages including Python, Perl, and Tcl.
Strong understanding of digital design verification and validation methodologies.
Excellent written and verbal communication skills.
Demonstrated technical leadership and cross-functional collaboration experience.
Preferred Qualifications
Experience working with multidisciplinary teams including architecture, analog, verification, and physical design engineers.
Experience optimizing designs for power, performance, and area requirements.
Experience leading post-silicon validation and production support activities.
Knowledge of industry-standard ASIC development and verification toolchains.
Benefits
Flexible 9/80 work schedule with every other Friday off.
Comprehensive medical, dental, and vision coverage.
401(k) retirement savings plan with company contributions.
Generous paid time off and company holidays.
Eligibility for short-term and long-term incentive programs.
Opportunity to work on innovative, cutting-edge semiconductor and digital design technologies
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Contact: [email protected]
This job and many more are available through The Judge Group. Find us on the web at www.judge.com
Skills
Python, Documentation
Experience
8+ yrs
Work arrangement
Yes
Skills from the listing
- Python
- Documentation
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