Lead/Principal Design Engineer

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Job Summary
We are looking for an experienced Senior ARM SoC Verification Engineer with 8–10 years of hands-on experience in functional verification of complex ARM-based SoCs, subsystems, and IPs.
The ideal candidate should have strong expertise in ARM architecture (ARMv7, ARMv8, and ARMv9), Generic Interrupt Controller (GICv3/GICv4), ARM Coherent Mesh Network (CMN), AMBA interconnect protocols, System Memory Management Unit (SMMU), and ARM CoreSight debug and trace architecture.
The candidate will be responsible for developing and executing comprehensive verification strategies, test plans, SystemVerilog/UVM and embedded C based verification environments, and functional coverage models to ensure the correctness, performance, and robustness of complex ARM-based SoC architectures.
Key Responsibilities
1. ARM Architecture and SoC Verification
Strong understanding of ARMv7, ARMv8, and ARMv9 architecture and associated system-level features.
Experience in verifying ARM-based multicore and heterogeneous SoC architectures.
Understanding of ARM exception levels (EL0–EL3), privilege modes, security states, TrustZone, MMU, caches, and memory ordering.
Knowledge of AArch32 and AArch64 execution states.
Verification of multicore coherency, cache hierarchy, memory consistency, and interconnect behavior.
Experience with system-level boot flows, reset sequences, power management, and low-power verification.
2. GIC Architecture Verification
Strong knowledge of ARM Generic Interrupt Controller architecture, specifically GICv3 and GICv4.
Experience verifying interrupt generation, routing, prioritization, and handling mechanisms.
Understanding of SPI, PPI, SGI, LPI, and virtual interrupt mechanisms.
Knowledge of Redistributor, Distributor, CPU Interface, and ITS architecture.
Experience with interrupt affinity routing, interrupt groups, security, and virtualization features.
Verification of interrupt delivery, acknowledgement, deactivation, and priority handling across multiple processing elements.
3. ARM CMN (Coherent Mesh Network)
Strong understanding of ARM CMN architecture and coherent interconnect concepts.
Understanding of cache coherency, snoop filtering, directory-based coherency, and home node behavior.
Experience with coherent transactions, cache maintenance operations, and memory ordering.
Verification of CHI-based coherent communication between processors, accelerators, memory controllers, and I/O devices.
Understanding of performance monitoring and debug capabilities in CMN.
4. AMBA Protocol Verification
Strong expertise in ARM AMBA protocols, including:
CHI (Coherent Hub Interface): Understanding of request, response, and data channels, transaction flow, coherency, ordering, snoop transactions, and retry mechanisms.
AXI / AXI4 / AXI5: Verification of read/write transactions, burst handling, outstanding transactions, ID management, ordering, backpressure, and error responses.
ACE / ACE-Lite: Understanding of cache coherency transactions, snoop channels, barriers, and coherent interconnect behavior.
AHB / AHB-Lite: Verification of bus transfers, arbitration, burst transactions, wait states, and response handling.
APB: Verification of peripheral transactions, setup/access phases, wait states, and error responses.
5. SMMU (System Memory Management Unit) Verification
Strong understanding of ARM SMMU architecture and address translation mechanisms.
Knowledge of stage-1 and stage-2 address translation.
Understanding of translation tables, stream IDs, substream IDs, and context descriptors.
Experience with translation lookaside buffers (TLBs), TLB invalidation, and translation faults.
Knowledge of device virtualization, DMA address translation, and memory protection.
Verification of access permissions, security attributes, and fault handling mechanisms.
6. ARM CoreSight Debug and Trace Architecture
Understanding of ARM CoreSight debug and trace architecture.
Knowledge of Embedded Trace Macrocell (ETM), Program Flow Trace (PFT), Trace Memory Controller (TMC), Trace Funnel, and Trace Replicator.
Understanding of Debug Access Port (DAP), JTAG, SWD, and memory-mapped debug access.
Experience with trace generation, trace routing, synchronization, and debug infrastructure.
Understanding of system-level debug and trace integration in multicore SoCs.
7. Functional Verification Methodology
Strong hands-on experience with SystemVerilog and UVM-based verification environments.
Development of reusable UVM testbenches, agents, sequences, drivers, monitors, scoreboards, and reference models.
Development of constrained-random and directed test scenarios.
Development of C based baremetal tests.
Functional coverage planning, implementation, and closure.
Assertion-based verification using SystemVerilog Assertions (SVA).
Debugging complex functional failures, waveform analysis, and root-cause identification.
Regression management, test optimization, and verification sign-off.
Experience in IP, subsystem, and full-chip SoC-level verification.
Required Technical Skills
Skill Area; Required Expertise
ARM Architecture
ARMv7, ARMv8, ARMv9
Interrupt Controller
GICv3, GICv4
Coherent Interconnect
ARM CMN
AMBA Protocols
CHI, AXI, ACE, APB, AHB
Memory Management
ARM SMMU
Debug Architecture
ARM CoreSight
Verification Language
SystemVerilog
Verification Methodology
UVM
Assertions
SVA
Scripting
Python / Perl / Shell
Required Qualifications and Experience
Bachelor's or Master's degree in Electronics and Communication Engineering, Electrical Engineering, Computer Engineering, or a related field.
8–10 years of experience in ASIC/SoC functional verification.
Strong hands-on experience in ARM-based SoC or subsystem verification.
Practical experience with multiple ARM architectural IPs and AMBA protocols.
Strong understanding of processor architecture, memory subsystem, interrupt architecture, and coherent interconnects.
Proven experience in developing UVM-based verification environments and achieving functional coverage closure.
Ability to independently own verification activities, debug complex issues, and drive verification sign-off.
Good to Have
Experience with ARM Neoverse or Cortex-A processor-based SoCs.
Knowledge of ARM virtualization extensions and TrustZone security architecture.
Experience with PCIe, CXL, DDR, LPDDR, and high-speed peripheral interfaces.
Knowledge of power management, clock/reset architecture, and low-power verification using UPF.
Experience with formal verification and protocol compliance verification.
Experience in post-silicon validation and silicon debug.
Familiarity with ARM Architecture Reference Manuals (ARM ARM), AMBA specifications, and ARM IP integration documentation.
Expected Competencies
Strong analytical and problem-solving skills.
Ability to understand complex SoC architecture and translate specifications into effective verification plans.
Independent ownership of verification IPs and subsystems.
Strong debugging and root-cause analysis capabilities.
Ability to collaborate with RTL designers, architects, and integration teams.
Technical leadership, mentoring, and review capabilities.
Ability to drive verification milestones and deliver quality results within project schedules.
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Skills
Python, Embedded C, Documentation