Public listing

Senior RTL design Engineer

Cadence Design Systems Hyderabad, Telangana, India (On-site)
  • Experience4-16 yrs
  • Work modeNo
  • ListedPosted 9 hours ago
  • SourceLinkedin

Role overview

About the role

Description supplied by the original job listing.

Cadence Hyderabad and PUNE
Join our world-class semiconductor design team and contribute to the development of next-generation SoCs, subsystems, and IP solutions.
Locations: Hyderabad & Pune, India
Experience: 4 to 16 Years
Role Summary
Lead the design and integration of complex SoC, subsystem, and IP blocks from architecture interpretation through RTL delivery and design closure. Drive micro-architecture development, RTL implementation, design reviews, and cross-functional collaboration with verification, physical design, DFT, firmware, and architecture teams.
Key Responsibilities
Own end-to-end RTL design and development of SoC, subsystem, and IP blocks.
Translate architecture requirements into detailed micro-architecture and implementation plans.
Develop high-quality RTL using Verilog/System Verilog.
Lead the design of interconnects, controllers, memory interfaces, datapaths, and protocol bridges.
Drive subsystem integration and resolve functionality, timing, and interface challenges.
Collaborate closely with Verification, Physical Design, DFT, and Architecture teams.
Support lint, CDC, RDC, synthesis, STA, low-power, and formal verification flows.
✅ Mentor junior engineers and contribute to design methodology improvements and reusable IP development.
Required Skills
🔹 Strong RTL design expertise using Verilog/SystemVerilog
🔹 Experience with SoC/IP development and micro-architecture design
🔹 Good understanding of AMBA protocols (AXI, AHB, APB)
🔹 Strong debugging and integration skills
🔹 Knowledge of DFT, CDC, RDC, synthesis, timing constraints, and low-power design
🔹 Scripting experience in Python, Perl, Tcl, or Shell
Preferred Skills
Experience with PCIe, DDR, NoC, Cache/Coherency, Security, or Safety designs
Exposure to UPF/CPF-based low-power methodologies
Silicon bring-up and formal verification experience
Experience leading design teams or owning major SoC subsystems
Qualifications: Bachelor's or Master's degree in Electronics, Electrical Engineering, Computer Engineering, or a related field.
If you're passionate about digital design and want to work on cutting-edge semiconductor technologies, we'd love to connect!
Interested candidates can share their resumes to [email protected]

Skills
Python

Experience
4-16 yrs

Work arrangement
No

Skills from the listing

  • Python

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