Digital Verification Senior Engineer

We Are
Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.
You Are
You have spent the last few years building verification environments that actually catch bugs before tapeout, and you know the difference between a testbench that looks complete and one that actually stresses the design. UVM is not just a framework you have heard about, it is something you have used to build real testbenches, debug real failures, and close coverage gaps that mattered.
You are comfortable reading a specification, asking the questions that are not written down, and turning that into a verification plan that makes sense. When a simulation fails at 3pm, you do not wait for someone to tell you what to do. You dig into waveforms, trace the issue, and figure out whether it is a test problem, an environment problem, or an actual design bug.
Protocols are not intimidating to you. Maybe you have worked with one already, maybe you have not, but you know how to read a spec, understand timing diagrams, and build checkers that enforce the rules. You are the kind of engineer who wants to get better, who asks good questions, and who does not need to be the smartest person in the room to contribute something real.
At Synopsys, you will work with people who have been doing this for years and who will help you grow.
What You'll Be Doing
Analyze design specifications and identify what needs to be verified, including functionality, interfaces, edge cases, and protocol compliance
Build and extend UVM-based verification environments in System Verilog, working alongside a technical lead to define architecture and reusable components
Write directed and constrained-random tests, implement functional checkers, and develop coverage models to track verification progress
Debug simulation failures by analyzing waveforms, logs, and coverage reports to isolate root causes in the testbench or design
Collaborate with design engineers to understand RTL changes and with the VIP team to integrate and leverage verification IP effectively
Contribute to test planning, code reviews, and process improvements that help the team close verification faster and with higher quality
Follow established verification methodologies and quality standards while identifying opportunities to improve flow efficiency
The Impact You Will Have
Your verification environments will catch critical design issues before they reach silicon, saving months of debug time and reducing tapeout risk
The test scenarios and checkers you build will directly improve functional coverage closure and give the team confidence in design correctness
Your collaboration with design engineers will surface ambiguities and corner cases early, leading to cleaner RTL and fewer late-stage surprises
The verification IP and reusable components you help develop will be leveraged across multiple projects, accelerating future verification efforts
Your contributions to test planning and coverage analysis will help the team make data-driven decisions about when a block is ready to integrate
The questions you ask and the gaps you identify will strengthen specifications and improve the overall quality of the product
Your willingness to learn new protocols and methodologies will expand the team's capability and enable support for more complex designs
What You'll Need
Bachelor's degree in Electronics Engineering, Electrical Engineering, or a closely related field
At least 3 years of hands-on experience in digital design verification
Proficiency in Verilog and System Verilog, with a working understanding of UVM methodology and testbench architecture
Experience writing and debugging testbenches, including constrained-random testing, functional coverage, and assertion-based verification
Ability to read and interpret design specifications, timing diagrams, and interface protocols
Experience with a standard protocol such as AXI, PCIe, USB, or Ethernet is a plus
Familiarity with simulation tools like VCS, Questa, or Xcelium is a plus
Who You Are
You can take a 50-page specification, pull out what matters for verification, and turn it into a test plan without needing someone to walk you through every line
When a test fails, you do not stop at "it is broken," you trace it back to the root cause and explain what went wrong in a way that helps the designer fix it quickly
You manage your own work without needing daily direction, you know what is blocking you, what is next, and when to ask for help
You communicate clearly in English, both in writing and in conversation, whether you are documenting a coverage gap or explaining a simulation failure in a team meeting
You are comfortable working with people across functions, design engineers who need clear bug reports, VIP teams who need integration feedback, and leads who need status without fluff
Learning a new protocol or verification technique does not intimidate you, it is just part of the job, and you are willing to put in the work to get up to speed
Rewards and Benefits
We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Experience
3+ yrs