Senior Principal Engineer - IP Design

Senior Principal Engineer - Digital Design
Job Description
Job Opportunity: Seeking highly motivated, energetic, team-oriented Individual Contributor driving roadmaps for Vision IP domain including complete IP portfolio, going deeper into logic design and architecting and developing Complex Vision IPs solutions. Working closely with experienced and motivated team of Global experts in Systems, SoC Design functions to address the design/architectural challenges in the context of the complex IP, algorithms and overall System level solutions. Work through a wide spectrum of skill from developing High level Specifications to actual design Implementation.
Key Responsibilities
Own and drive Roadmaps for complete IP domains portfolio within global R&D team.
Perform benchmarks against other industry players and ensure differentiating features for our customer with high level of innovation.
Architect and Design complex IP across a range of protocols required for Automotive Self Driving Vehicles (ADAS) both Vision and Radar, In-Vehicle networks, Gateway Systems, Fail Safe Subsystems (ASIL-D) etc.
Own and Lead IP from Concept till IP Design and Development achieving final design performance in integrated system within aggressive, market driven schedules.
Ensure quality adherence during all stages of the IP development cycle and carry out a thorough analysis of existing processes, recommend and implement the process improvements to ensure ‘Zero Defect’ designs and drive and mentor teams towards that.
Key Skills
Self-starter with 12-15 years of hands-on experience to Architect and Design complex IP design / Sub-system with minimal supervision.
Custom Processing pipeline Designs with key image and signal processing functions like those needed for Vision processing.
Experience in microcontroller architecture, Cache, protocols like AHB/AMBA,AXI.
Extensive hands on knowledge of HDLs (Verilog/VHDL), Scripting languages (Perl, Tcl), C/C++ for hardware modeling.
Understanding of end to end IP development flow including complex CDC, RDC constructs, IP Synthesis, DFT ATPG coverage.
Have worked on Testbench and Testplan development closely with the verification team.
Hands on work on pre silicon validation using FPGA/Emulation Board would be a significant added advantage.
Key Soft Skills
Proficient skills in both written and verbal communication. Can articulate well.
Has a sense of Ownership and engages everyone with Trust and Respect.
Should demonstrate Emotional Intelligence and Leadership values with ability to work well as a part of team both local and remote or multisite.
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