ASIC Engineer, Implementation

Meta is building custom silicon to power the next generation of infrastructure supporting AI, augmented reality, and virtual reality at scale. As an ASIC Implementation Engineer on the Infrastructure Silicon team, you will contribute to the physical implementation of complex custom ASICs from RTL through tape-out, working across synthesis, place-and-route, timing closure, and signoff. In this role, you will collaborate with design, architecture, and verification teams to deliver high-performance, power-efficient silicon that meets the demanding requirements of Meta's data center and compute infrastructure.
ASIC Engineer, Implementation Responsibilities:
Run Logic/Physical Synthesis using advanced optimization techniques and generate an optimized Gate Level Netlist for Timing, Area, and Power
Debug the timing/area/congestion issues and work with RTL and physical designers to resolve them
Perform power estimation at RTL and gate level, and identify power reduction opportunities
Run Formal Verification checks between RTL and gate-level netlist, and debug the aborts, inconclusive, and logic equivalency failures
Perform RTL Lint and work with the designers to create waivers
Perform RTL DFT analysis and improve the DFT coverage for stuck-at faults
Develop timing constraints for RTL synthesis and PrimeTime-STA for the blocks and the top-level including SoC
Analyze the inter-block timing and come up with I/O budgets for the various partition blocks
Developing automation scripts and methodology for all FE tools including (Lint, CDC, RDC, Synthesis, STA, Power)
Work closely with the design engineers, DV engineers, emulation engineers in supporting them with the handoff tasks
Interact with Physical Design Engineers and provide them with timing/congestion feedback
Minimum Qualifications:
2+ years of experience as a Front-End Synthesis & Integration Engineer
Experience with RTL synthesis and design optimization for power, performance, and area
Knowledge of front-end and back-end ASIC tools
Experience with RTL design using SystemVerilog or other HDL
Experience managing multiple design releases and working with cross-functional teams to support and debug timing, area, and power issues
Experience with communicating across functional internal teams and vendors
Preferred Qualifications:
Knowledge of Physical Design flow such as Floorplanning, CTS, Routing
Knowledge of STA signoff and understanding of AOCV, POCV
Good Understanding of Timing/physical libraries, SRAM Memories
Experience with EDA tools and scripting languages (Python, TCL) used to build tools and flows
Experience with Design Compiler, Spyglass, PrimeTime, Formality or equivalent tools
Experience with low power techniques for reducing power
Experience in SOC Design Integration and Front-End Implementation
About Meta:
Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today—beyond the constraints of screens, the limits of distance, and even the rules of physics.
Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity or sales incentives, if applicable. In addition to base compensation, Meta offers benefits. Learn more about benefits at Meta.

Work arrangement
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