DDR / UCIe Design Verification Engineer

Job Title: Engineer DDR / UCIe DV
Location: Hyderabad
Experience: 4 6 Years
Employment Type: Contract
Job Summary
We are looking for an experienced Digital Design Verification (DV) Engineer with strong hands-on experience in UVM, SystemVerilog, DDR/LPDDR, and UCIe protocol verification. The candidate will be responsible for developing verification environments, test plans, test cases, and validating RTL/gate-level designs.
Must-Have Skills
UVM verification & UVM environment development
SystemVerilog
DDR / DDR3 / DDR4 / LPDDR / UCIe
AMBA AXI / AHB / APB protocols
RTL & Gate-Level Simulation
Test Plan & Testcase Development using C / Assembly / SystemVerilog
Functional & Code Coverage / Performance Verification
Python / Perl / Shell scripting
Key Responsibilities
Develop and maintain UVM-based verification environments.
Define test plans and develop comprehensive test cases.
Verify designs at RTL and gate level.
Perform protocol, performance, coverage, and use-case verification.
Verify DDR/LPDDR and UCIe interfaces.
Work with AXI, AHB, and APB protocols.
Debug simulation failures and collaborate with design teams for issue resolution.
Develop regression and automation scripts using Python, Perl, or Shell.
Preferred Candidate
Candidates with strong hands-on experience in DDR/UCIe verification, UVM, SystemVerilog, and AMBA protocols are highly preferred.
Immediate Joiners / Short Notice Candidates Preferred.
share resume to haritha1@galaxyitech.com

Work arrangement
No