CPU Core Design Verification Manager

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.
At Tenstorrent, we build open, state of the art compute for real workloads and real developers.
You will lead our Bangalore-based CPU Core Design Verification team, driving both the technical strategy and the people leadership behind verification of our high-performance, out-of-order RISC-V CPUs. You will manage a team of core-level verification engineers, partner closely with our Santa Clara and Austin sites, and own delivery of core verification from architecture definition through tapeout readiness.
This role is based out of Bangalore, India, with regular collaboration across our globally distributed CPU organization.
We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.
Who You Are
You bring 15+ years in CPU verification or closely related digital design, including at least 7+ years directly managing or leading a verification team.
You have deep hands-on experience with core-level verification for high-performance, out-of-order CPUs, and can still get into RTL, waveforms, and regressions when it matters.
You know out-of-order CPU microarchitecture in depth, and can guide a team through complex ISA and microarchitectural verification challenges.
You have led testbench development and verification methodology (UVM and/or CVM), and can set technical direction for reusable infrastructure across a team.
You are experienced in managing engineers across a range of seniority levels, including hiring, mentoring, and career growth.
You are comfortable operating across time zones, coordinating daily with counterparts and leadership in Santa Clara and Austin.
You are comfortable driving cross-functional debug and prioritization across design, DV, emulation, and post-silicon teams, including triaging and unblocking P0 issues.
You are comfortable using AI-assisted verification workflows to improve debug, stimulus creation, and coverage analysis across your team, while applying strong engineering judgment to validate results.
What We Need
Build, lead, and grow the Bangalore CPU Core Design Verification team, including hiring, mentoring, and performance management.
Own functional verification strategy and execution for CPU core features, ISA behavior, and microarchitectural scenarios on our high-performance, out-of-order RISC-V cores.
Drive verification methodology and infrastructure decisions (UVM/CVM), balancing reusability with the pace of a fast-moving CPU program.
Partner with core, cluster, and chip-level DV leads in Santa Clara and Austin to align coverage goals, schedules, and escalation paths across sites.
Represent the Bangalore verification team in planning and tapeout readiness reviews, and drive closure of open bugs and coverage gaps against milestones.
Balance hands-on technical involvement (debug, code/testplan review, architecture discussions) with the people-management responsibilities of running a growing team.
Champion the team's adoption of AI-assisted tooling for triage, stimulus generation, and coverage analysis, in coordination with Tenstorrent's broader DV tooling efforts.
What You Will Learn
How Tenstorrent designs and verifies high-performance RISC-V CPU cores and clusters across a globally distributed organization.
How to scale a verification team and its infrastructure across core, cluster, and chip-level environments spanning multiple sites.
Techniques for spanning pre-silicon, emulation, and post-silicon verification with shared stimulus and methodology.
How Tenstorrent applies AI across the DV lifecycle — from test planning and stimulus through regression debug, triage, and coverage analysis — using workflows designed to keep context tight and outputs auditable.
How to build and run a high-performing verification organization inside a fast-growing, technically ambitious silicon company.

Work arrangement
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