DFT Engineer | 4+ Yrs

Company Description LeadIC Design Pvt Ltd is a VLSI engineering company focused on accelerating semiconductor innovation through full-stack chip design expertise. Founded in 2018, the company has become a trusted partner for global semiconductor leaders, supporting the complete chip development lifecycle from circuits and RTL to physical design, verification, and characterization. With engineering teams in India and Canada, LeadIC delivers high-quality design services tailored to product-driven teams and scalable offshore development centers. The organization emphasizes strong engineering ownership, quality-driven execution, and flexible partnership models that adapt to diverse technical and business needs. LeadIC builds long-term technical partnerships aimed at enabling successful, reliable silicon products.
Role Description This is a full-time hybrid role for a DFT Engineer (4+ years of experience), based in Bengaluru with flexibility for partial work from home. The DFT Engineer will plan and implement design-for-test structures, including scan insertion, test compression, and BIST for complex SoCs and ASICs. Day-to-day responsibilities include developing and validating test architectures, generating and optimizing test patterns, collaborating with RTL, physical design, and verification teams, and performing test coverage analysis and debugging. The role involves creating and maintaining test specifications, ensuring testability requirements are met, and supporting bring-up, failure analysis, and yield improvement activities. The DFT Engineer will also contribute to process improvements, documentation, and knowledge sharing within the team.
Qualifications
Candidates should possess strong skills in Testing and Functional Testing, with a solid understanding of test methodologies and quality assurance practices for semiconductor devices.
Candidates should possess practical experience in Test Engineering and Test Execution, including planning, running, and analyzing hardware and simulation-based test suites.
Candidates should possess skills in designing and managing Test Cases, including specification, coverage tracking, and regression strategies for DFT-related verification.
Hands-on experience with DFT tools and flows (scan insertion, ATPG, boundary scan, MBIST, LBIST) and familiarity with major EDA tools.
Strong understanding of digital design, RTL, synthesis, timing concepts, and testability constraints in advanced process nodes.
Bachelor’s or Master’s degree in Electrical/Electronics Engineering or a related field, with 4+ years of relevant DFT experience.
Ability to collaborate effectively with cross-functional teams, communicate clearly in written and spoken English, and work in a structured, detail-oriented manner.
Experience with semiconductor product bring-up, failure debug, and yield improvement is an advantage.

Work arrangement
No