PD CAD Flow Development Engineer

Experience: 5–10 Years
Location: Bengaluru
Employment Type: Full-Time
About the Role
We are looking for an experienced CAD / EDA Flow Development Engineer with strong hands-on expertise in the Netlist-to-GDSII / Physical Design implementation flow.
The ideal candidate will have a strong understanding of the complete ASIC Physical Design flow and hands-on experience with EDA/CAD tools, flow development, automation, tool integration and methodology development.
In this role, you will work closely with the Physical Design team to develop, deploy, customize and optimize CAD applications and implementation flows, enabling engineers to efficiently execute complex designs from netlist through physical implementation and GDSII.
This is a highly technical role requiring a combination of Physical Design knowledge, EDA tool expertise, scripting and CAD flow development.
Key Responsibilities
Develop, implement and maintain CAD/EDA flows supporting the complete Netlist-to-GDSII implementation process.
Work closely with Physical Design engineers to understand application/tool requirements and translate them into robust, scalable CAD flows and solutions.
Configure, integrate and deploy EDA tools used across the Physical Design flow.
Develop and optimize flows covering Floorplanning, Placement, Clock Tree Synthesis (CTS), Routing, Physical optimization, Timing analysis, Extraction, Physical verification, Sign-off, GDSII generation
Develop automation frameworks and scripts to improve design productivity, flow efficiency and implementation quality.
Integrate multiple EDA tools into a unified and automated implementation flow.
Develop flow wrappers, runsets, configuration files, scripts and automation utilities.
Debug tool/flow issues, identify root causes and work with EDA vendors when required.
Customize and optimize tool configurations, commands and methodologies based on project requirements.
Develop reusable CAD methodologies and flows across multiple designs and technology nodes.
Support Physical Design teams during implementation and sign-off by troubleshooting tool, flow and methodology issues.
Analyze flow performance, runtime, memory usage and implementation results to identify opportunities for optimization.
Develop checks, reports and dashboards to monitor QoR, timing, congestion, utilization and implementation health.
Support migration and deployment of CAD flows across different technology nodes and EDA tool versions.
Maintain flow documentation, methodology guidelines and user documentation.
Work with Physical Design, STA, RTL, DFT, Verification and Foundry/Technology teams to ensure smooth implementation.
Required Skills & Experience
Bachelor's or Master's degree in ECE, EE, VLSI, Computer Science or related discipline.
5–12 years of experience in CAD/EDA, Physical Design methodology or flow development.
Strong understanding of the complete ASIC Netlist-to-GDSII flow.
Hands-on experience with major Physical Design stages including Floorplanning, Placement, CTS, Routing, Timing optimization, Physical optimization, Extraction, Sign-off, GDSII generation
Strong hands-on experience with EDA/CAD tools used in Physical Design.
Experience with tools from Synopsys, Cadence and/or Siemens EDA.
Strong scripting/programming skills in Tcl/Python/Shell/Perl
Experience developing automated implementation flows and CAD utilities.
Good understanding of LEF/DEF, Liberty, Verilog netlists, SDC, SPEF, GDSII and technology files.
Strong understanding of timing, physical implementation and QoR optimization.
Experience debugging complex flow/tool issues.
Ability to work closely with PD engineers and convert their requirements into scalable CAD solutions.
EDA Tools – Preferred
Hands-on experience with one or more of the following:
Physical Design
Synopsys ICC2 / Fusion Compiler
Cadence Innovus
Timing / Sign-off
Synopsys PrimeTime
Cadence Tempus
Physical Verification
Siemens Calibre
Synopsys IC Validator
Synthesis
Synopsys Design Compiler
Cadence Genus
Experience across multiple EDA vendors will be an advantage.
Good to Have
Experience with advanced technology nodes, preferably 16nm and below.
Experience supporting large and complex SoC designs.
Experience with multi-corner/multi-mode implementation flows.
Knowledge of MCMM, OCV/AOCV/POCV and timing closure.
Experience with flow migration across technology nodes.
Experience developing GUI/web-based CAD applications or internal EDA tools.
Knowledge of Linux/Unix environments.
Experience working directly with EDA tool vendors.
Exposure to CI/CD, regression frameworks or automated flow validation.
Experience building reusable PD methodology frameworks.

Work arrangement
No