SOC Debug Verification Engineer II

Overview
Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate engineers to help achieve that mission.
The Compute Silicon & Manufacturing Engineering (CSME) organization within SCHIE is responsible for design, development, manufacturing and packaging of Microsoft's state-of-the-art computer chips, notably the Azure Cobalt. Our solutions provide sustainable strategic advantage to Microsoft and enable our customers to achieve more.
As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the Verification & Validation team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure.
Responsibilities
The candidate for this position will be expected and able to complete the following responsibilities:
Own verification of Design for Debug (DFD) SoC level flows including Task planning and schedule estimation, proactively identifying and removing roadblocks and finding ways to make the team more efficient
Develop verification strategy, requirements, environments, tools, and methodologies
Get good knowledge on overall debug architecture, understand customer use models, and understand interactions with other parts of the SOC, with the platform, and with software
Apply your knowledge of verification principles and techniques and your judgement to write test plans and implement them by developing tests, test generators, test benches, checkers, coverage, and other verification collateral
Run tests, debug failures to root cause, and recommend fixes
Apply your growth mindset to learn and adapt in a complex and dynamic environment
Engage with partners to drive continuous improvement to both the design, to verification plans/collateral, and to methodology to prevent, reduce, and/or find bugs sooner, more easily, or more reliably
Provide technical guidance, coaching, and mentorship to other engineers in your areas of expertise
Apply your One Microsoft mentality to collaborate with and influence architects, logic designers, post-silicon validators, other verification engineers, and IP and tool providers
Delight your customers by providing high quality results on schedule
Provide technical leadership with respect and integrity
Apply your expertise towards supporting the post-silicon validation plans, tests, and debug of your area
Apply industry leading generative AI solutions to verification work
Qualifications
Required Qualifications:
6+ years of pre-silicon SOC or subsystem or IP verification experience.
Candidate should have at least a bachelor’s or master’s degree in electrical, Electronics, Computer Engineering, Computer Science or a related degree
5+ years of verification experience working on CPU/SOC designs, with 2+ years of design for debug verification experience
Preferred Qualifications
Experience with SOC DFD verification for a full product cycle from definition to silicon, including writing SOC level test plans, developing tests, debugging failures and coverage signoff
Demonstrated expertise in industry standard DFD architectural protocols such as JTAG interface, hardware triggers, breakpoints and tracing and hands-on experience in ARM Core Sight debug components (DAP, CTI ETM, TPIU, Funnel/Replicators)
Familiarity with ARM AMBA protocols (AXI/ACE/CHI preferred)
Experience enabling and/or utilizing debug features in post-silicon
Proficient communication, collaboration and teamwork skills and ability to contribute to diverse and inclusive teams
Experience planning verification tasks, estimating and assigning tasks, coordinating with customers and suppliers, and executing the plan
Proficient leadership skills
Passion for improving verification efficiency
Experience with Agile software practices
This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled.
Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.

Work arrangement
No