Live opening · Posted 21 days ago

MTS-Signal/Power Integrity Engineer

Tsavorite Scalable Intelligence · Greater Bengaluru Area (Hybrid)
Linkedin No
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At a glance

The key details from the original listing.

Posted 21 days ago
CompanyTsavorite Scalable Intelligence
LocationGreater Bengaluru Area (Hybrid)
Work modeNo
SourceLinkedin
Listed21 days ago

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About the role

Description supplied by the original job listing.

MTS Signal/Power Integrity Engineer
Bangalore
Founded in 2023,by Industry veterans HQ in California,US
Location: Greater Bengaluru Area
(
Company Description:
We are product based startup. The products are chipsets and intelligent machines that enable scalable enterprises AI, streaming video intelligence, training trillion parameter models, and fine-tuning LLMs, allowing enterprises to improve productivity with advanced solutions. We are looking for exceptional talent and leadership to join our organization, the world’s first company developing Agentic Silicon for powering the future of AI.
We are pioneering a new era in AI innovation focused on accelerating the
adoption of end-to-end enterprise AI, from the edge to Zettascale systems.
Our cutting-edge Software and composable silicon Chiplets will transform the way AI models are Trained, Deployed, and Scaled.
"Join Our Growing Team!"
We are building a world-class team to drive innovation in AI Silicon & Software and hiring for below position in Bangalore.
Basic Qualifications
Strong academic/technical background in electrical engineering; Bachelor’s is required; Master’s preferred.
8-11+ years of experience supporting or developing complex SoC/silicon products for Server and Networking applications.
8-11+ years of hands-on high-speed SI/PI design, simulation, and measurement experience.
Have a proven track record with defining hardware system constraints and high-speed technology roadmaps.
Cross-functional design mentality with the silicon design community to develop systems.
Proven track record solving problems independently, preferably as a tech lead.
Required Experience
Familiar with SI and PI design challenges for PCIe Gen3/4 and/or 100G Ethernet PCB and interconnects
simulation experience with Cadence/Ansys/ADS/ toolsets
EM modeling of connector structures
High-speed SERDES channel simulation, and equalization
Expertise in multi-level and NRZ signaling, COM, BER, jitter analysis
Familiar with VNA, TDR, real-time and sub-sampling
Working knowledge of PCB fabrication limits and trade-offs
PI experience a strong plus.
Familiar with industry-standard such as PCISIG, and IEEE802.3, especially Electrical sections.
Proficiency in using high-speed lab equipment such as BERT, VNA
Contact:
Uday
Mulya Technologies
muday_bhaskar@yahoo.com
"Mining The Knowledge Community"

Work arrangement
No

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