Package Architect

Package Architect
www.tsavoritesi.com
Bangalore
Founded in 2023,by Industry veterans HQ in California,US
Location: Greater Bengaluru Area
Company Description:
We are product based startup. The products are chipsets and intelligent machines that enable scalable enterprises AI, streaming video intelligence, training trillion parameter models, and fine-tuning LLMs, allowing enterprises to improve productivity with advanced solutions. We are looking for exceptional talent and leadership to join our organization, the world’s first company developing Agentic Silicon for powering the future of AI.
We are pioneering a new era in AI innovation focused on accelerating the
adoption of end-to-end enterprise AI, from the edge to Zettascale systems.
Our cutting-edge Software and composable silicon Chiplets will transform the way AI models are Trained, Deployed, and Scaled.
"Join Our Growing Team!"
We are building a world-class team to drive innovation in AI Silicon & Software and hiring for below position in Bangalore
Key Links to Include
Official Website: tsavoritesi.com
LinkedIn Page: Tsavorite Scalable Intelligence | LinkedIn
Recent News: Tsavorite Emerges with $100M in Orders & 10x Performance (Forbes)
https://www.businesswire.com/news/home/20251110678526/en/Tsavorite-Scalable-Intelligence
Senior Package designer Job Description :
Qualifications:
More than 16+ years of experience in the flip chip BGA package design
Experience working on the Large Formfactor, high layer count designs, Stack-up definition, Bump and ball map definition, Package outline drawings
Very good understanding of the package design rules as well as design for manufacturing and successful tape out of multiple designs.
Knowledge of Package level signal integrity and power integrity.
Worked on High speed Serdes(PCIE Gen6, 112-224 G Ethernet) and memory interface like DDR5, LPDDR and HBM.
Mentor Xpedition experience is preferred.
Responsibilities:
Responsible for the package design of the Leading edge AI products for Tsavorite.
Responsible for the feasibility studies for the new IP definition and Package design concepts.
Owning the substrate layout design from start to end and taping out multiple products
Co-design between Silicon, package and board.
Collaborate closely with the Signal integrity, power integrity leads, PCB design, Mechanical and thermals to optimize the design to meet the product requirements.
Interface with the OSAT/Packaging suppliers to understand the design rules, review the package design, meet DFM requirements and Documentation of BOM.
Contact:
Uday
Mulya Technologies
muday_bhaskar@yahoo.com
"Mining The Knowledge Community"

Work arrangement
No