Senior Physical Design Engineer

Company Description THINSIL is a semiconductor company focused on advancing technology through innovation and collaboration. Founded on March 1, 2018, the company delivers cutting-edge solutions to leading global customers including AMD, ADI, EMM, Qualcomm, Siliconch, and Samsung. THINSIL operates at the frontier of semiconductor excellence, working on complex design and development challenges that impact next-generation products. Team members are encouraged to contribute ideas, solve technical problems, and help shape the future of high-performance semiconductor technology.
Role Description The Senior Physical Design Engineer role at THINSIL is a full-time, on-site position based in Bengaluru. This role involves owning and executing physical design tasks such as floorplanning, placement, clock tree synthesis, routing, timing closure, and power optimization for complex ASIC and SoC projects. The engineer will collaborate closely with RTL, logic, and verification teams to ensure smooth handoff, design integrity, and successful tape-out. Daily responsibilities include analyzing design constraints, running and debugging STA, performing physical verification, resolving design and layout issues, and preparing documentation and reports. The person in this role is expected to provide technical leadership, mentor junior engineers, and contribute to continuous improvement of design flows and methodologies.
Qualifications
Strong Physical Design skills, including experience with floorplanning, placement, CTS, routing, timing closure, and power/area optimization.
5+years of experience in Physical Design Engineering
Experience in Physical Verification, including DRC, LVS, ERC, and familiarity with industry-standard verification tools and sign-off flows.
Proficiency in Logic Design and Circuit Design, with a solid understanding of digital design fundamentals, timing, and signal integrity.
Hands-on experience with RTL Design, including interpreting and constraining RTL, and collaborating with front-end teams for implementation.
Practical knowledge of EDA tools (e.g., Cadence, Synopsys, Mentor) and scripting skills in languages such as TCL, Python, or Perl to automate flows.
Bachelor’s or Master’s degree in Electrical Engineering, Electronics, or a related field, with several years of relevant industry experience in ASIC/SoC physical design.
Strong analytical and problem-solving abilities, attention to detail, and the capacity to work effectively in a collaborative, fast-paced environment.
Experience with advanced technology nodes and interaction with global customers or cross-functional teams is highly beneficial.

Work arrangement
No